Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein

A wafer-scale semiconductor integrated circuit device, comprising:

• a wafer-scale semiconductor substrate having a main surface including a central portion and peripheral portion, wherein the main surface has substantially a circular shape;
• a plurality of memory blocks formed on the main surface of the wafer-scale semiconductor substrate, wherein each of the memory blocks occupies substantially a rectangular area on the main surface, and wherein the memory blocks have substantially a same area size on the main surface and are substantially provided at the central portion of the main surface;
• and
• means for relieving defects in the memory blocks, said means including a plurality of memory circuits each of which is formed at the peripheral portion of the main surface of the wafer-scale semiconductor substrate, wherein each of the memory circuits occupies substantially a rectangular area on the main surface, and wherein each of the memory circuits occupies a smaller area than that of each of the memory blocks, the memory circuits being used for relieving defects in the memory blocks by storing data in the memory circuits instead of in the memory blocks.

A wafer-scale semiconductor integrated circuit device, comprising:

• a wafer-scale semiconductor substrate having a main surface including a central portion and peripheral portion, wherein the main surface has substantially a circular shape;
• a plurality of memory blocks formed on the main surface of the wafer-scale semiconductor substrate, wherein each of the memory blocks occupies substantially a rectangular area on the main surface, and wherein the memory blocks have substantially a same area size on the main surface and are substantially provided at the central portion of the main surface;
• and
• means for relieving defects in the memory blocks, said means including a plurality of memory circuits each of which is formed at the peripheral portion of the main surface of the wafer-scale semiconductor substrate, wherein each of the memory circuits occupies substantially a rectangular area on the main surface, wherein each of the memory circuits occupies a smaller area than that of each of the memory blocks and wherein the memory circuits include memory arrays and decoder circuits.

A wafer-scale semiconductor integrated circuit device, comprising:

• a wafer-scale semiconductor substrate having a main surface including a central portion and peripheral portion, wherein the main surface of the wafer-scale semiconductor substrate has substantially a circular shape;
• a plurality of memory blocks being formed on the main surface of the wafer-scale semiconductor substrate and each having substantially a same area size on the main surface, wherein the memory blocks are substantially provided at the central portion of the main surface;
• and
• a plurality of preliminary memory circuits formed at the peripheral portion of the main surface of the wafer-scale semiconductor substrate, wherein each of the preliminary memory circuits occupies a smaller area than that of a memory block, and wherein each of the preliminary memory circuits includes a memory array and a decoder circuit.

A wafer-scale semiconductor integrated circuit device, comprising:

• a wafer-scale semiconductor substrate having a main surface including a central portion and peripheral portion, wherein the mean surface has substantially a circular shape;
• a plurality of memory blocks formed on the main surface of the wafer-scale semiconductor substrate, wherein each of the memory blocks occupies substantially a rectangular area on the main surface, wherein the memory blocks have substantially s same area size on the main surface and are substantially provided at the central portion of the main surface, and wherein the memory blocks are comprised of a plurality of memory mats;
• and
• means for relieving defects in the memory blocks, said means including a plurality of memory circuits each of which is formed at the peripheral portion of the main surface of the wafer-scale semiconductor substrate, wherein each of the memory circuits occupies substantially a rectangular area on the main surface, wherein each of the memory circuits occupies a smaller area than that of each of the memory blocks, and wherein a memory capacity of the memory circuit is substantially the same as that of the memory mat.

A wafer-scale semiconductor integrated circuit device, comprising:

• a wafer-scale semiconductor substrate having a main surface including a central portion and peripheral portion, wherein the main surface has substantially a circular shape;
• a plurality of memory blocks formed on the main surface of the wafer-scale semiconductor substrate, wherein each of the memory blocks occupies substantially a rectangular area on the main surface, and wherein the memory blocks have substantially a same area size on the main surface and are substantially provided at the central portion of the main surface;
• and
• means for relieving defects in the memory blocks, said means including a plurality of memory circuits each of which is formed at the peripheral portion of the main surface of the wafer-scale semiconductor substrate, wherein each of the memory circuits occupies substantially a rectangular area on the main surface, wherein each of the memory circuits occupies a smaller area than that of each of the memory blocks, and wherein a memory capacity of a memory block is substantially the same as that of a predetermined number of the memory circuits.

A wafer-scale semiconductor integrated circuit device, comprising:

• a wafer-scale semiconductor substrate having a main surface including a central portion and peripheral portion, wherein the main surface of the wafer-scale semiconductor substrate has substantially a circular shape;
• a plurality of memory blocks being formed on the main surface of the wafer-scale semiconductor substrate and each having substantially a same area size on the main surface, wherein the memory blocks are substantially provided at the central portion of the main surface, and wherein each of the memory blocks is comprised of a plurality of memory mats;
• and
• a plurality of preliminary memory circuits formed at the peripheral portion of the main surface of the wafer-scale semiconductor substrate, wherein each of the preliminary memory circuits occupies a smaller area than that of a memory block, wherein the preliminary memory circuits are used for relieving defects in the memory mats, and wherein a memory capacity of a preliminary memory circuit is substantially the same as that of a memory mat.