Self-aligned thin film transistor

A semiconductor device comprising:

• a substrate;
• a first electrode region overlying the substrate, the first electrode region lying within a first plane;
• a second electrode region overlying the substrate and electrically isolated from the first electrode region, the second electrode region lying within the first plane;
• a first patterned dielectric layer overlying the substrate and extending above the first and second electrode regions, the first patterned dielectric layer having a perimeter and a sidewall;
• a semiconductive sidewall spacer adjacent to the sidewall of the first patterned dielectric layer, and formed around the perimeter of the first patterned dielectric layer, the semiconductive sidewall spacer being electrically coupled to the first and the second electrode regions;
• a second dielectric layer adjacent to the semiconductive sidewall spacer;
• a control electrode adjacent the second dielectric layer wherein the control electrode is electrically isolated from the first and the second electrode regions and the semiconductive sidewall spacer.

A semiconductor device comprising:

• a substrate;
• a first electrode region overlying the substrate;
• a first dielectric layer overlying the first electrode region;
• a second electrode region overlying the substrate;
• an opening in the first dielectric layer wherein the opening is divided into a first lateral half and a second lateral half wherein a portion of the first electrode region is intersected in only the second lateral half of the opening, and a portion of the second electrode region is intersected in only the first lateral half of the opening, the opening having a perimeter and a sidewall;
• a semiconductive sidewall spacer adjacent to the sidewall of the opening, and formed around the perimeter of the opening, the semiconductive sidewall spacer being electrically coupled to the first electrode region in only the second lateral half of the opening, and the semiconductive sidewall spacer being electrically coupled to the second electrode region in only the first lateral half of the opening;
• a second dielectric layer adjacent to the semiconductive sidewall spacer;
• a control electrode adjacent to the second dielectric layer, and electrically isolated from the first and the second electrode regions and the semiconductive sidewall spacer.

A semiconductor device comprising:

• a substrate;
• a first electrode region overlying the substrate, the first electrode region lying within a first plane;
• a second electrode region overlying the substrate and electrically isolated from the first electrode region, the second electrode region lying within the first plane;
• a first dielectric layer overlying the first and the second electrode regions;
• an opening in the first dielectric layer wherein the opening intersects a portion of the first electrode region and a portion of the second electrode region, the opening having a perimeter and a sidewall;
• a semiconductive sidewall spacer adjacent to the sidewall of the opening, and formed around the perimeter of the opening, the semiconductive sidewall spacer being electrically coupled to the first and the second electrode regions;
• a second dielectric layer adjacent to the semiconductive sidewall spacer;
• a control electrode adjacent to the second dielectric layer, and electrically isolated from the first and the second electrode regions and the semiconductive sidewall spacer.

A semiconductor device comprising:

• a substrate;
• a first dielectric layer overlying the substrate;
• a first electrode region overlying the first dielectric layer, the first electrode region lying within a first plane and having a sidewall;
• a second electrode region overlying the first dielectric layer and electrically isolated from the first electrode region, the second electrode region lying within the first plane and having a sidewall;
• an opening in the first dielectric layer wherein the opening intersects a portion of the first electrode region and a portion of the second electrode region to define the respective sidewalls thereof, the opening having a perimeter;
• a semiconductive sidewall spacer formed around the perimeter of the opening, the semiconductive sidewall spacer being electrically coupled to the sidewall of the first electrode region and the sidewall of the second electrode region;
• a second dielectric layer adjacent to the semiconductive sidewall spacer;
• a control electrode adjacent to the second dielectric layer, and electrically isolated from the first and the second electrode regions and the semiconductive sidewall spacer.

A semiconductor device comprising:

• a semiconductive sidewall spacer having a channel region formed therein, the semiconductive sidewall spacer being further characterized as an annular region;
• a first electrode region self-aligned to the channel region;
• a second electrode region self-aligned to the channel region;
• a dielectric layer adjacent to the semiconductive sidewall spacer;
• and
• a control electrode adjacent to the dielectric layer wherein the control electrode is electrically isolated from the first and the second electrode regions and the semiconductive sidewall spacer.

A semiconductor device comprising:

• a semiconductive sidewall spacer having a channel region formed therein, the semiconductive sidewall spacer being further characterized as an annular region;
• a first electrode region self-aligned to the channel region;
• a second electrode region self-aligned to the channel region;
• a dielectric layer adjacent to the semiconductive sidewall spacer;
• a control electrode adjacent to the dielectric layer wherein the control electrode is electrically isolated from the first and the second electrode regions and the semiconductive sidewall spacer;
• and
• a transistor having a gate, wherein said control electrode and said gate are of continuous polysilicon.