Semiconductor memory device and method of formation

A method for forming a random access memory structure wherein the method comprises:

• forming a first vertical transistor having a first current electrode for conducting a ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region;
• forming a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor to form a first storage node, a second current electrode overlying the first current electrode of the second transistor, the second current electrode of the second transistor functioning as a first bit line to provide data external to the random access memory structure, a channel region separating the first and second current electrodes, and a gate electrode coupled to a first word line conductor wherein the first word line conductor selectively turns on the second transistor;
• and
• forming a first load device wherein the first load device has a first terminal coupled to the first storage node and a second terminal coupled to a power supply voltage terminal.

A method for forming a random access memory structure wherein the method comprises:

• forming a first N-channel vertical transistor having a first current electrode for carrying a ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region;
• forming a first P-channel vertical transistor overlying the first N-channel vertical transistor, the first P-channel vertical transistor having a first current electrode coupled to the second current electrode of the first N-channel vertical transistor to form a first storage node, a second current electrode overlying the first current electrode of the first N-channel vertical transistor, the second current electrode of the first P-channel vertical transistor being coupled to a power supply voltage terminal, a channel region separating the first and second current electrodes of the first P-channel vertical transistor, and a gate electrode coupled the gate electrode of the first N-channel vertical transistor;
• and
• forming a first N-channel pass transistor wherein the first N-channel pass transistor has a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line conductor, and a gate electrode coupled to a first word line conductor.

A method for forming a static random access memory cell wherein the method comprises:

• forming a first vertical transistor having a first current electrode for carrying a ground potential, a second current electrode overlying the first current electrode, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region, the first vertical transistor being an N-channel transistor;
• forming a second vertical transistor overlying the first vertical transistor, the second vertical transistor having a first current electrode coupled to the second current electrode of the first vertical transistor to form a first storage node, a second current electrode overlying the first current electrode of the second transistor, the second current electrode of the second vertical transistor being coupled to a first bit line to provide data external to the random access memory cell, a channel region separating the first and second current electrodes, and a gate electrode coupled to a word line conductor wherein the first word line conductor selectively makes the second transistor conduct current, the second vertical transistor being an N-channel transistor;
• forming a first resistive load device wherein the first resistive load device has a first terminal coupled to the first storage node and a second terminal coupled to a power supply voltage terminal;
• forming a third vertical transistor laterally separated from the first vertical transistor, the third vertical transistor having a first current electrode for conducting a ground potential, a second current electrode coupled to the gate electrode of the first vertical transistor, a channel region separating the first current electrode and the second current electrode, and a gate electrode adjacent the channel region which is coupled to the second current electrode of the first vertical transistor, the third vertical transistor being an N-channel transistor;
• forming a fourth vertical transistor overlying the third vertical transistor, the fourth vertical transistor having a first current electrode coupled to the second current electrode of the third vertical transistor to form a second storage node, a second current electrode coupled to a second bit line to provide data external to the random access memory cell, a channel region separating the first and second current electrodes, and a gate electrode coupled to the word line conductor wherein the word line conductor selectively makes the fourth vertical transistor conduct current, the fourth vertical transistor being an N-channel transistor;
• and
• forming a second resistive load device wherein the second resistive load device has a first terminal coupled to the second storage node and a second terminal coupled to a power supply voltage terminal.