Method of formation of transistor and logic gates

A method for forming a logic device comprising the steps of:

• forming a plurality of N rank ordered stacked transistors, where N is an integer greater than one, each transistor except a first transistor thereof overlying a transistor of immediately lower rank, each transistor having a first current electrode, a second current electrode, and a control electrode wherein for each of the stacked transistors either the first current electrode overlies the second current electrode or the second current electrode overlies the first current electrode, each transistor except the first transistor thereof having one of either the first current electrode or the second current electrode electrically coupled to a transistor of immediately lower rank;
• further electrically coupling the first and second current electrodes and control electrode of each of the plurality of stacked transistors corresponding to a predetermined logic device structure to form the logic device;
• and
• electrically coupling an output conductor to one current electrode of the N transistors wherein the one current electrode of the N transistors is an electrode other than the second current electrode of the Nth rank ordered transistor and the first current electrode of the first rank ordered transistor.

A method for forming a semiconductor device comprising the steps of:

• providing a substrate having a surface;
• forming a first transistor at least partially overlying the surface of the substrate, the first transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region;
• forming a second transistor overlying the first transistor and fully overlying the surface of the substrate, the second transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region;
• forming a conductive interconnect region overlying the substrate, the conductive interconnect region being electrically coupled to the first electrode of the second transistor wherein the conductive interconnect region provides an output voltage from the semiconductor device;
• and
• electrically coupling the first electrode of the second transistor to the second electrode of the first transistor.

A method for forming a semiconductor device comprising the steps of:

• providing a substrate having a surface;
• forming a first transistor overlying the surface of the substrate, the first transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region wherein one of either the first current electrode, the second current electrode, or the channel region is formed by selective growth from the substrate, the first transistor being made of a first conductivity type;
• forming a second transistor overlying the first transistor, the second transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region wherein one of either the first current electrode, the second current electrode, or the channel region is formed by selective growth from the substrate, the second transistor being of a second conductivity type;
• forming an electrical contact layer overlying the substrate wherein the electrical contact layer is coupled to the second electrode of the first transistor and provides an output voltage which indicates a logic voltage of the second electrode of the first transistor;
• and
• electrically coupling the first electrode of the second transistor to the second electrode of the first transistor.

A method for forming a vertically stacked N-input logic device, where N is an integer, the method comprising the steps of:

• providing a substrate;
• forming a plurality of (N+1) rank ordered stacked transistors overlying the substrate, each transistor except a first transistor thereof overlying a transistor of immediately lower rank, each transistor having a first current electrode, a second current electrode, at least one control electrode, a channel region, and a gate dielectric layer wherein for each of the stacked transistors either the first current electrode overlies the second current electrode or the second current electrode overlies the first current electrode, each transistor except the first transistor thereof having one of either the first current electrode or the second current electrode electrically coupled to a transistor of immediately lower rank;
• forming N control electrodes adjacent one of the channel regions of one of the plurality of (N+1) rank ordered stacked transistors;
• and
• electrically coupling the first and second current electrodes and control electrode of each of the plurality of (N+1) rank ordered stacked transistors corresponding to a selected logic device structure to form the vertically stacked N-input logic device.

A method for forming at least two transistors, comprising the steps of:

• providing a substrate;
• forming a first current electrode overlying the substrate;
• forming a channel region overlying the first current electrode;
• forming a second current electrode overlying the channel region;
• forming N gate electrodes adjacent the channel region where N is an integer and is greater than one the first current electrode, second current electrode, channel region, and N gate electrodes forming a first transistor;
• forming a second transistor overlying the first transistor wherein the second transistor has a current electrode coupled to the second current electrode of first transistor;
• and
• forming a metallic region which connects the first current electrode of the second transistor to the second current electrode of the first transistor.