# US 5,307,477 A · Two-level cache memory system

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- Number: US 5,307,477 A
- Document ID: US5307477A
- Status: Granted
- Kind: A
- Application number: 08/059,715
- Filed: 1993-05-10
- Granted: 1994-04-26
- Earliest claimed: 1989-12-01
- Assignees: MIPS Computer Systems, Inc.
- Inventors: George S. Taylor; P. Michael Farmwald; Timothy P. Layman; Huy X. Ngo; Allen W. Roberts
- Web page: https://patentgrep.com/patent/US5307477A

## CPC

- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1045: associated with a data cache
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

## Claims

### Claim 1

A cache memory system comprising:
processing means for generating a virtual address;
a primary cache memory, comprising:
primary cache tag means containing a plurality of primary virtual tags, the primary cache tag means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding primary cache virtual tag to the processing means;
primary instruction cache means containing a plurality of instructions and a first plurality of virtual tags, the primary instructions and a first plurality of virtual tags, the primary instruction cache means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding instruction from the plurality of instructions to the processing means; and
primary data cache means containing a second plurality of primary virtual tags and a plurality of data units, the primary data cache means also connected to receive at least a portion of the virtual address from the processing means and in response to supply a corresponding data unit from the plurality of data units to the processing means;
translation means connected to receive the virtual address form the processing and translate the virtual address into a physical address; and
a secondary cache memory, comprising:
secondary cache tag means containing a plurality of secondary virtual tags, the secondary cache tag means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding secondary virtual tag to the processing means; and
secondary cache means containing a plurality of instructions and data units, the secondary cache means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding instruction or data unit from the plurality of instructions and data to the processing means;
wherein the primary cache memory employs a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.

### Claim 2 (depends on 1)

A cache memory system as in claim 1 wherein the secondary cache means further includes a reserved section for storing secondary physical tags.

### Claim 3 (depends on 1)

A cache memory system as in claim 1 wherein the secondary cache memory includes a reserved portion for storing translation lookaside buffer information.

### Claim 4

A computing system comprising:
a processing unit for processing data under control of instructions;
translation means coupled to the processing unit for translating a virtual address into a physical address;
primary cache tag means coupled to receive at least a portion of the virtual address from the processing unit for supplying primary cache virtual tags to the processing unit;
secondary cache tag means coupled to receive at least a portion of the physical address from the translation means for supplying secondary cache virtual tags to the processing unit;
primary instruction cache means coupled to receive at least a portion of the virtual address from the processing unit for supplying instructions to the processing unit;
primary data cache means coupled to receive at least a portion of the virtual address from the processing unit for supplying data to the processing unit; and
secondary cache means coupled to receive at least a portion of the physical address from the translation means for supplying instructions and data to the processing unit;
wherein the primary cache tag means, the primary instruction cache means, and the primary data cache means are part of a primary cache memory, the primary cache memory employing a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.

### Claim 5 (depends on 4)

A computing system as in claim 4 wherein the secondary cache tag means also includes physical tags.