Digital to analog converter for sigma delta modulator

A sigma delta modulator, comprising:

• a first integrator controlled by a modulator clock for receiving an analog input signal;
• a second integrator coupled to said first integrator and controlled by said modulator clock;
• an analog to digital converter coupled to said second integrator for generating a digital output signal in response to said analog input signal;
• a digital to analog converter coupled to said analog to digital converter, said digital to analog converter receives said digital output signal from said analog to digital converter and provides said first and second integrators with a corresponding analog feedback signal, said digital to analog converter comprising:
• a plurality of main capacitors, each main capacitor representing a specific value of said digital output signal received by said digital to analog converter;
• dynamic element matching circuit to randomly select among said main capacitors according to said digital output signal;
• self calibration circuit to match said main capacitors to each other such that said main capacitors have identical values;
• and
• a decimation filter for eliminating undesirable noise in said digital output signal.

A method of calibrating capacitors of a digital to analog converter within a sigma delta modulator, comprising the steps of:

• grounding an analog input signal;
• decreasing a clock rate of a pseudo-random number generating capacitor selector within the digital to analog converter below a clock rate of the sigma delta modulator;
• determining a statistical variance in a digital output signal generated by the sigma delta modulator;
• and
• adjusting a value of each capacitor such that each capacitor has an identical value in order to minimize said statistical variance.