Pipelined combination and vector signal processor

A digital signal processor integrated circuit comprising:

• a first data input bus;
• first input leads coupled to said first input data bus;
• a second data input bus;
• a first set of multiplexers coupled to said first data input bus;
• a second set of multiplexers coupled to said second data input bus;
• a first arithmetic processor coupled to outputs of said first set of multiplexers;
• a number of latch stages coupled to outputs of said second set of multiplexers, said number corresponding to a number of clock cycles for sequencing data through said first arithmetic processor;
• a second arithmetic processor having first inputs coupled to outputs of said first arithmetic processor and second inputs coupled to outputs of said latch stages;
• a data output bus coupled to outputs of said second arithmetic processor;
• output leads coupled to said data output bus;
• control input leads coupled to said integrated circuit;
• control means, having control inputs coupled to said control input leads of said integrated circuit and control outputs coupled to said first and second sets of multiplexers and said first and second arithmetic processors, for selecting a first combination of said multiplexers for a fast FFT operation in said first and second arithmetic processors in response to a first control signal on said control input leads, and for selecting a second combination of said multiplexers for a block multiply operation in one of said first and second arithmetic processors in response to a second control signal on said control input leads;
• an internal data bus coupled between said output data bus and said first data input bus;
• and
• means, coupled to said internal data bus, for selectively providing data from said output leads or said outputs of said second arithmetic processor to one of said first input leads and said first set of multiplexers.

A digital signal processor integrated circuit comprising:

• a first data input bus;
• a second data input bus;
• input leads coupled to said first and second data input buses;
• a first set of multiplexers coupled to said first data input bus;
• a second set of multiplexers coupled to said second data input bus;
• a first arithmetic processor coupled to outputs of said first set of multiplexers;
• a number of latch stages coupled to outputs of said second set of multiplexers, said number corresponding to a number of clock cycles for sequencing data through said first arithmetic processor;
• a second arithmetic processor having first inputs coupled to outputs of said first arithmetic processor and second inputs coupled to outputs of said latch stages;
• a data output bus coupled to outputs of said second arithmetic processor;
• output leads coupled to said data output bus;
• control input leads coupled to said integrated circuit;
• control means, having control inputs coupled to said control input leads of said integrated circuit and control outputs coupled to said first and second sets of multiplexers and said first and second arithmetic processors, for selecting a first combination of said multiplexers for a fast FFT operation in said first and second arithmetic processors in response to a first control signal on said control input leads, and for selecting a second combination of said multiplexers for a block multiply operation in one of said first and second arithmetic processors in response to a second control signal on said control input leads;
• said control means, in response to each of a plurality of control signals, controls said first and second arithmetic processors to perform a function specified by said control signals on a stream of data following each of said control signals;
• scale factor generator means, coupled to said outputs of said second arithmetic processor, for producing scale factors corresponding to the shifting of data between inputs to said first arithmetic processor and said outputs of said second arithmetic processor;
• means, coupled to said scale factor generator mean, for combining a plurality of said scale factors to produce a total scale factor;
• a cumulative scale factor memory for storing said total scale factor;
• a beginning of pass (BOP) input lead for receiving a BOP signal indicating a new set of data in said stream of data;
• and
• means, responsive to said BOP signal, for clearing said cumulative scale factor memory.

A digital signal processor integrated circuit comprising:

• a first data input bus;
• a second data input bus;
• first means, coupled to said first data input bus, for receiving a plurality of serial data groupings and providing a single, parallel data group at a first data path;
• second means, coupled to said second data input bus, for receiving a plurality of serial data groupings and providing a single, parallel data group at a second data path;
• a first arithmetic processor coupled to said first data path;
• a number of latch stages coupled to said second data path, said number corresponding to a number of clock cycles for sequencing data through said first arithmetic processor;
• a second arithmetic processor having first inputs coupled to outputs of said first arithmetic processor and second inputs coupled to outputs of said latch stages;
• a data output bus coupled to outputs of said second arithmetic processor;
• output leads coupled to said data output bus;
• control input leads coupled to said integrated circuit;
• and
• control means, having control inputs coupled to said control input leads of said integrated circuit and control outputs coupled to said first and second means and said first and second arithmetic processors, for selecting a first combination of data for a fast FFT operation in said first and second arithmetic processors in response to a first control signal on said control input leads, and for selecting a second combination of data for a block multiply operation in one of said first and second arithmetic processors in response to a second control signal on said control input leads.