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US 5,302,871 AGranted
Delay circuit
AssigneeKabushiki Kaisha Toshiba
InventorsYukiya Matsuzaki, Yasushi Sato, Masaharu Kawauchi
Life of this patent
Estimating the term…
Abstract
The present invention relates to a delay circuit comprising an input terminal, a first MOS transistor series including at least two MOS transistors of a first conductivity type whose current paths are connected to one another and whose gates are connected to the input terminal, a second MOS transistor series including at least two MOS transistors of a second conductivity type whose current paths are connected to one another and whose gates are connected to the input terminal, an output terminal connected to a connection point of the first and second MOS transistor series, a first power supply serving as a current supplier of the first MOS transistor series, and a second power supply serving as a current discharger of the second MOS transistor series.
Claims18
A delay circuit comprising:
- an input terminal;
- a first MOS transistor series including at least two MOS transistors of a first conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a second MOS transistor series including at least two MOS transistors of a second conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- an output terminal connected to a connection point of said first and second MOS transistor series;
- a first power supply serving as a current supplier to said first MOS transistor series;
- and
- a second power supply serving as a current discharger of said second MOS transistor series.
4 more elements
A delay circuit comprising:
- an input terminal;
- a first MOS transistor series including at least two MOS transistors of a first conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a second MOS transistor series including at least two MOS transistors of a second conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a third MOS transistor series including at least two MOS transistors of the first conductivity type whose current paths are connected to one another and whose gates are connected to a connection point of said first and second MOS transistor series;
- a fourth MOS transistor series including at least two MOS transistors of the second conductivity type whose current paths are connected to one another and whose gates are connected to the connection point of said first and second MOS transistor series;
- an output terminal connected to a connection point of said third and fourth MOS transistor series;
- a first power supply serving as a current supplier to said first and third MOS transistor series;
- and
- a second power supply serving as a current discharger of said second and fourth MOS transistor series.
6 more elements
A delay circuit comprising:
- an input terminal;
- a first MOS transistor series including at least two MOS transistors of a first conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a second MOS transistor series including at least two MOS transistors of a second conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a third MOS transistor series including at least two MOS transistors of the first conductivity type whose current paths are connected to one another and whose gates are connected to a connection point of said first and second MOS transistor series;
- a fourth MOS transistor series including at least two MOS transistors of the second conductivity type whose current paths are connected to one another and whose gates are connected to the connection point of said first and second MOS transistor series;
- an output terminal connected to a connection point of said third and fourth MOS transistor series;
- a first power supply serving as a current supplier to said first and third MOS transistor series;
- and
- a second power supply serving as a current discharger of said second and fourth MOS transistor series,
- wherein said first power supply is connected to a connection point of any two of the current paths of the MOS transistors of said first MOS transistor series, and said second power supply is connected to a connection point of any two of the current paths of the MOS transistors of said fourth MOS transistor series.
7 more elements
A delay circuit comprising:
- an input terminal;
- a first MOS transistor series including at least two MOS transistors of a first conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a second MOS transistor series including at least two MOS transistors of a second conductivity type whose current paths are connected to one another and whose gates are connected to said input terminal;
- a third MOS transistor series including a plurality of MOS transistors of the first conductivity type whose current paths are connected to one another, gates of some of said plurality of MOS transistors being connected to a connection point of said first and second MOS transistor series, and others of said plurality of MOS transistors being always turned on;
- a fourth MOS transistor series including a plurality of MOS transistors of the second conductivity type whose current paths are connected to one another, gates of some of said plurality of MOS transistors being connected to the connection point of said first and second MOS transistor series, and others of said plurality of MOS transistors being always turned on;
- an output terminal connected to a connection point of said third and fourth MOS transistor series;
- a first power supply serving as a current supplier to said first and third MOS transistor series;
- and
- a second power supply serving as a current discharger of said second and fourth MOS transistor series.
6 more elements
Dependencies are inferred from the claim text.