An electrical system for transferring data signals concurrently between a host device and a plurality of pen based portable computers, each of the plurality of pen based computers including a battery, a display and an unlighted pen for handwritten input of information on the display, at least one of the pen based computers being received by a multiple computer receptacle device, the electrical system comprising:
- a first signal generating circuit, the first signal generating circuit forming a portion of the multiple computer receptacle device and providing a first signal indicative of the at least one pen based computer received by the multiple computer receptacle device;
- a first signal receiving circuit, the first signal receiving circuit forming a portion of the host device and providing an output signal in response to the first signal;
- a second signal generating circuit, the second signal generating circuit forming a portion of the host device and providing a second signal for polling the pen based computers and for performing a security check with respect thereto;
- a second signal receiving circuit, the second signal receiving circuit forming a portion of the at least one pen based computer and generating an output signal in response to the second signal;
- a third signal generating circuit, the third signal generating circuit forming a portion of the at least one pen based computer and providing a third signal for polling the host device and for performing a security check with respect thereto;
- a third signal receiving circuit, the third signal receiving circuit forming a portion of the host device and generating at least first and second output signals in response to the third signal;
- a first look-up table memory circuit, the first look-up table memory circuit forming a portion of the host device and having stored therein logic data corresponding to a plurality of first identification/password logic codes, each of the first identification/password codes corresponding to a respective pen based computer;
- a fourth signal generating circuit, the fourth signal generating circuit forming a portion of the host device and providing a fourth signal corresponding to at least one of the first identification/password codes;
- a second look-up table memory circuit, the second look-up table memory circuit forming a portion of the at least one pen based computer and having stored therein logic data corresponding to a second identification/password logic code;
- a fourth signal receiving and comparator circuit, the fourth signal receiving and comparator circuit forming a portion of the at least one pen based computer and providing an output signal in response to the fourth signal, the PG,74 second look-up table memory circuit being electrically coupled to the fourth signal receiving and comparator circuit, the fourth signal receiving and comparator circuit comparing the second identification/password code logic data stored in the second look-up table memory circuit with logic data corresponding to the fourth signal, and providing an output signal in response to the comparison thereof;
- a fifth signal generating circuit, the fifth signal generating circuit forming a portion of the at least one pen based computer and providing a fifth signal in response to the output signal of the fourth signal receiving and comparator circuit, the fifth signal corresponding to the second identification/password code logic data stored in the second look-up table memory circuit of the at least one pen based computer;
- a fifth signal receiving and comparator circuit, the fifth signal receiving and comparator circuit forming a portion of the host device and comparing the first identification/password code logic data stored in the first look-up table memory circuit with logic data corresponding to the fifth signal, and providing an output signal in response thereto, the output signal being provided to the second signal generating circuit, the second signal generating circuit being responsive to the output signal and providing the second signal in response thereto;
- an identification/password code selection circuit, the identification/password code selection circuit forming a portion of the host device and being electrically coupled to the first look-up table memory circuit, the identification/password code selection circuit generating third identification/password codes for storage by the first look-up table memory circuit and for substitution in the first look-up table memory circuit of the first identification/password signals;
- a sixth signal generating circuit, the sixth signal generating circuit forming a portion of the host device and providing a sixth signal corresponding to the third identification/password code generated by the identification/password code selection circuit;
- a sixth signal receiving circuit, the sixth signal receiving circuit forming a portion of the at least one pen based computer and providing an output signal in response thereto, the output signal corresponding to the third identification/password code and being provided to the second look-up table memory circuit, the second look-up table memory circuit storing the output signal corresponding to the third identification/password code as logic data in substitution for the second identification/password code logic data;
- a first data memory circuit, the first data memory circuit forming a portion of the at least one pen based computer and having stored therein logic data inputted to the pen based computer by the user thereof;
- a first data transmission circuit, the first data transmission circuit forming a portion of the at least one pen based computer and electrically coupled to the first data memory circuit for transmitting first data signals corresponding to the logic data stored in the first data memory circuit, the first data signals being transmitted by the first data transmission circuit a first time and a second time;
- a first data receiving circuit, the first data receiving circuit forming a portion of the host device and receiving the first data signals;
- a first data buffer memory circuit, the first data buffer memory circuit forming a portion of the host device and coupled to the first data receiving circuit and storing therein the first data signals transmitted the first time as first pen based computer transmitted logic data, and storing therein the first data signals transmitted the second time as second pen based computer transmitted logic data;
- a first file length and content check circuit, the first file length and content check circuit forming a portion of the host device and electrically coupled to the first data buffer memory circuit, the first file length and content check circuit comparing the first pen based computer transmitted logic data with the second pen based computer transmitted logic data and providing an output signal in response to the comparison thereof;
- a seventh signal generating circuit, the seventh signal generating circuit forming a portion of the host device and providing a seventh signal in response to the output signal of the first file length and content check circuit;
- a seventh signal receiving circuit, the seventh signal receiving circuit forming a portion of the at least one pen based computer and providing an output signal in response to the seventh signal, the output signal being provided to the first data memory circuit, the first data memory circuit erasing the logic data stored therein in response to the output signal of the seventh signal receiving circuit;
- a second data memory circuit, the second data memory circuit forming a portion of the host device and having stored therein logic data inputted to the host device by the operator thereof;
- a second data transmission circuit, the second data transmission circuit forming a portion of the host device and electrically coupled to the second data memory circuit for transmitting second data signals corresponding to the logic data stored in the second data memory circuit, the second data signals being transmitted by the second data transmission circuit a first time and a second time;
- a second data receiving circuit, the second data receiving circuit forming a portion of the at least one pen based computer and receiving the second data signals;
- a second data buffer memory circuit, the second data buffer memory circuit forming a portion of the at least one pen based computer and coupled to the second data receiving circuit and storing therein the second data signals transmitted the first time as first host device transmitted logic data and storing therein the second data signals transmitted the second time as second host device transmitted logic data;
- a second file length and content check circuit, the second file length and content check circuit forming a portion of the at least one pen based computer and electrically coupled to the second data buffer memory circuit, the second file length and content check circuit comparing the first host computer transmitted logic data with the second host computer transmitted logic data and providing an output signal in response to the comparison thereof;
- an eighth signal generating circuit, the eighth signal generating circuit forming a portion of the at least one pen based computer and providing an output signal in response to the output signal of the second file length and content check circuit;
- an eighth signal receiving circuit, the eighth signal receiving circuit forming a portion of the host device and providing an output signal in response to the eighth signal;
- a ninth signal generating circuit, the ninth signal generating circuit forming a portion of the host device and providing a ninth signal in response to the output signal of the eighth signal receiving circuit;
- a ninth signal receiving circuit, the ninth signal receiving circuit forming a portion of the at least one pen based computer and providing a disable signal in response to the ninth signal, the disable signal being provided to the second signal receiving circuit, the second signal receiving circuit being responsive thereto;
- a keyboard, the keyboard being coupled to the host device and being provided for entering logic data to the second data memory circuit;
- an input/output circuit, the input/output circuit being coupled to the keyboard and to the second data memory circuit;
- a display, the display being electrically coupled to and responsive to the output signals of the third signal receiving circuit, the first file length and content check circuit, the eighth signal receiving circuit and the ninth signal receiving circuit;
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- a discharge and recharge circuit, the discharge and recharge circuit forming a portion of the multiple computer receptacle device and being electrically coupled to the at least one pen based computer and responsive to the ninth signal.