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US 5,301,197 AGranted
Bit error ratio detector
AssigneeNEC Corporation
InventorsAkio Yamada, Katsuhiro Sasaki
Life of this patent
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Abstract
An error ratio detector according to the present invention, which detects the error ratio of error correction-coded data with a syndrome, reduces the error pulse occurrence probability by using only the errors in an M (<N) period within each block (of N bits) as errors for calculating the error ratio, and thereby makes it possible to assess the bit error ratio in a high BER region even where blocks are rather long.
Claims5
An error detector for calculating the error ratio from error correction-coded data, comprising:
- syndrome generating means for generating a syndrome by receiving said data;
- error location signal generating means for generating from said syndrome an error location signal indicating the bit location where each bit error has occurred;
- timing pulse generating means for generating a timing pulse in a predetermined period within each block of data;
- error pulse generating means for generating an error pulse if said error location signal is generated in said predetermined period;
- and
- error ratio detecting means for calculating the bit error ratio (BER) according to the number of said error pulses in predetermined blocks.
3 more elements
Dependencies are inferred from the claim text.