Multi-staged charge-pump with staggered clock phases for providing high current capability

A multiple-series charge pump comprising a plurality of series charge pumps, said multiple-series charge pump for converting a first voltage to a second voltage with reduced noise distribution and capacitor short tolerance, each of said series charge pumps comprising:

• a plurality of diode-connected NMOSFETs connected in series, the first NMOSFET in the series being coupled to said first voltage and the last NMOSFET in said series being coupled to said second voltage, each of the remaining NMOSFETs in said series being coupled at its gate to a capacitor, wherein each of said capacitors can be sized to generate a different loadline characteristic for said multiple series charge pump, said series having its adjoining NMOSFETs driven by different such that no two adjoining NMOSFETs are driven at the same time;
• a series resistor coupled between said first NMOSFET and its adjoining NMOSFET to limit return current to a predetermined level and to provide a voltage drop from said first voltage across said series resister;
• clocking means coupled to said multiple series charge pump for providing said different clocks, said clocking means having all NMOSFET buffers to guard against return current latch-up;
• and
• a clock pass gate coupled to the last NMOSFET of last NMOSFET when tapping off from the second to last NMOSFET of said series to form an output for a third voltage, said third voltage being lower than said second voltage, wherein said third voltage generates higher current than said second voltage.

A charge pump network for converting a first voltage to a second voltage with reduced noise distribution and reduced output ripples, said charge pump network comprising:

• an oscillator means for generating a plurality of input clocks, each of said plurality of input clocks staggered in time with respect to each other;
• delay means coupled to receive one input clock of said plurality of input clocks, said delay means for generating a plurality of non-overlapping staggered delayed clocks from said one input clock with a predetermined delay between each of said staggered delayed clocks such that a first staggered delayed clock is delayed to form a second staggered delayed clock;
• clock driver means coupled to receive said plurality of non-overlapping staggered delayed clocks, said clock driver means for generating a switching clock for each of said plurality of staggered delayed clocks, each of said switching clocks having a higher current capability than the corresponding staggered delayed clock from said plurality of staggered delayed clocks;
• a multiple staged charge pump coupled to receive said plurality of switching clocks from said clock driver means, each stage of said multiple staged charge pump having multiple series connected in parallel, each series having a plurality of diode-connected n-channel MOSFETs, the first n-channel MOSFET in each series being coupled to said first voltage, each of the remainder of said n-channel MOSFETs in each series being coupled to a capacitor at its gate, each series of said each stage having its adjoining n-channel MOSFETs driven by different switching clocks from said clock driver means such that no two adjoining n-channel MOSFETs are driven at the same time;
• and
• second voltage means coupled to the last n-channel MOSFET in each series of said multiple-series charge pump for generating said second voltage from combining all of said series after said first voltage is switch-regulated through said multiple staged charge pump.