Clock distribution circuit with active de-skewing

A clock distribution circuit comprising

• a plurality of output drivers connected to receive a clock signal and to distribute said clock signal on a plurality of outward signal paths to a plurality of clock recipients,
• comparison means, connected to receive a return signal on a plurality of inward return paths from said plurality of clock recipients and also connected to receive a reference signal, for comparing the phase of said return signal on each of said return paths with the phase of said reference signal, said inward return paths being parallel to and substantially equal in length to corresponding outward signal paths, and
• delay means, including a plurality of controllable delay elements located on both said outward signal paths and said inward return paths, for adjusting signal delays on said paths in response to a result of said comparing by said comparison means until the phase of said return signal on each inward return path is substantially equal to the phase of said reference signal, said signal delay on each outward signal path being equal to said signal delay on the corresponding inward return path, whereby said clock signal arrives at said plurality of clock recipients with substantially equal phase,
• further comprising an input receiver located on each of said return paths, said input receiver having plural input buffers with different logic level transition points, each input buffer having an input connected to said return path, each input buffer also having an output connected to programmable means for selecting one of said input buffers for coupling to said comparison means.

A clock distribution circuit comprising

• a plurality of output drivers connected to receive a clock signal and to distribute said clock signal on a plurality of outward signal paths to a plurality of clock recipients,
• comparison means, connected to receive a return signal on a plurality of inward return paths from said plurality of clock recipients and also connected to receive a reference signal, for comparing the phase of said return signal on each of said return paths with the phase of said reference signal, said inward return paths being parallel to and substantially equal in length to corresponding outward signal paths, and
• delay means, including a plurality of controllable delay elements located on both said outward signal paths and said inward return paths, for adjusting signal delays on said paths in response to a result of said comparing by said comparison means until the phase of said return signal on each inward return path is substantially equal to the phase of said reference signal, said signal delay on each outward signal path being equal to said signal delay on the corresponding inward return path, whereby said clock signal arrives at said plurality of clock recipients with substantially equal phase,
• further comprising means receiving a system reset signal for providing a reset output signal, said reset output signal being active whenever said system reset signal is active and also whenever said signal delays are still being adjusted by said delay means in response to said result of said comparing by said comparison means.

A clock distribution circuit comprising

• driver means for providing multiple copies of a clock signal on multiple outputs connected to first conductive traces so as to distribute said clock signal to a plurality of clock recipients, and
• de-skewing logic means for measuring propagation times of said clock signal along said conductive traces from each output to the corresponding clock recipient and for compensating for differences in said propagation times to ensure that said clock signal arrives at said plurality of clock recipients with substantially equal phase, said de-skewing logic means including
• (a) means for receiving return signals on multiple inputs connected to second conductive traces from said plurality of clock recipients, each second trace being parallel to and substantially equal in length to a corresponding first trace to which said second trace is connected near a corresponding clock recipient,
• (b) means for providing a reference clock signal,
• (c) comparison means with inputs coupled to said receiving means and to said reference clock providing means for comparing the phases of said return signals with respect to the phase of said reference clock signal, and
• (d) a plurality of voltage-controlled delay elements connected to said driver means and to said return signal receiving means so as to provide time delays to signals on said first and second traces, each pair of delay elements associated with corresponding first and second traces being responsive to a control voltage output from said comparison means as a result of comparing said return signal on said associated second trace,
• wherein said receiving means includes a plurality of input buffers connected to said second conductive traces and a multiplexer connected between said input buffers and said comparison means, said multiplexer responsive to a selection control signal so as to select one of said input buffers for coupling to said comparison means.

A clock distribution circuit comprising

• driver means for providing multiple copies of a clock signal on multiple outputs connected to first conductive traces so as to distribute said clock signal to a plurality of clock recipients, and
• de-skewing logic means for measuring propagation times of said clock signal along said conductive traces from each output to the corresponding clock recipient and for compensating for differences in said propagation times to ensure that said clock signal arrives at said plurality of clock recipients with substantially equal phase, said de-skewing logic means including
• (a) means for receiving return signals on multiple inputs connected to second conductive traces from said plurality of clock recipients, each second trace being parallel to and substantially equal in length to a corresponding first trace to which said second trace is connected near a corresponding clock recipient,
• (b) means for providing a reference clock signal,
• (c) comparison means with inputs coupled to said receiving means and to said reference clock providing means for comparing the phases of said return signals with respect to the phase of said reference clock signal, and
• (d) a plurality of voltage-controlled delay elements connected to said driver means and to said return signal receiving means so as to provide time delays to signals on said first and second traces, each pair of delay elements associated with corresponding first and second traces being responsive to a control voltage output from said comparison means as a result of comparing said return signal on said associated second trace,
• wherein said comparison means includes a single common phase comparator for multiple driver means and a multiplexer connected to an input of said common phase comparator, said multiplexer having inputs connected to receiving means of plural second conductive traces and having a selection input, said multiplexer responsive to a signal on said selection input to select one of said second conductive traces to be coupled to said common phase comparator.

A clock distribution circuit comprising

• driver means for providing multiple copies of a clock signal on multiple outputs connected to first conductive traces so as to distribute said clock signal to a plurality of clock recipients, and
• de-skewing logic means for measuring propagation times of said clock signal along said conductive traces from each output to the corresponding clock recipient and for compensating for differences in said propagation times to ensure that said clock signal arrives at said plurality of clock recipients with substantially equal phase, said de-skewing logic means including
• (a) means for receiving return signals on multiple inputs connected to second conductive traces from said plurality of clock recipients, each second trace being parallel to and substantially equal in length to a corresponding first trace to which said second trace is connected near a corresponding clock recipient,
• (b) means for providing a reference clock signal,
• (c) comparison means with inputs coupled to said receiving means and to said reference clock providing means for comparing the phases of said return signals with respect to the phase of said reference clock signal, and
• (d) a plurality of voltage-controlled delay elements connected to said driver means and to said return signal receiving means so as to provide time delays to signals on said first and second traces, each pair of delay elements associated with corresponding first and second traces being responsive to a control voltage output from said comparison means as a result of comparing said return signal on said associated second trace,
• further comprising means receiving a system reset signal for providing a reset output signal, said reset output signal being active whenever said system reset signal is active and also whenever changes to said control voltage output from said comparison means are still being made as a result of said comparing by said comparison means.