Synchronous logarithmic amplifier
AssigneeAnalog Devices, Inc.
InventorBarrie Gilbert
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AssigneeAnalog Devices, Inc.
InventorBarrie Gilbert
Estimating the term…
A synchronous progressive-compression type logarithmic amplifier includes one or two channels of amplifier/limiter stages and a corresponding multi-stage synchronous demodulator circuit to provide low noise and/or low power operation as well as other useful operational modes. A preferred embodiment of the invention includes two channels in which the input of a first amplifier stage in each channel forms a logarithmic amplifier input. The synchronous demodulator circuit is realized as a number of multiplier stages each having a first input coupled to the output of a corresponding amplifier stage in the first channel, a second input coupled to the output of a corresponding amplifier stage in the second channel, and a current output. A current summing bus is coupled to the current outputs of each of the multiplier stages, and forms the logarithmic amplifier output. The output voltage of the logarithmic amplifier can be used directly to provide the instantaneous logarithm of the input signal, or can be filtered to provide the logarithm of the envelope of the input signal.
A logarithmic amplifier (40) comprising:
A logarithmic amplifier (50) comprising:
An amplification method comprising the steps of:
Dependencies are inferred from the claim text.