Method and apparatus for maintaining deterministic behavior in a first synchronous system which responds to inputs from nonsynchronous second system

A structure for maintaining deterministic behavior in a first system whose operations are synchronized by clock pulses of a first clock, where the first system responds to input signals from a second system and operations of the second system are not synchronized by the look pulses of the first clock, the structure comprising:

• clock control means for receiving clock stop commands and clock restart commands and correspondingly stopping and restarting the supply of clock pulses to the first system;
• blocking means, coupled to the second system and the clock control means, for blocking the transfer of behavior-changing input signals from the second system into the first system while clock signals are supplied to the first system, said behavior-changing input signals being ones which can induce changes in the behavior of the first system once their introduction into the first system is recognized by the first system;
• and
• transfer coordinating means, for issuing clock stop commands to the clock control means at prespecified cycles of the first clock, for transferring prespecified ones of the behavior-changing input signals from the second system into the first system while clock signals are not supplied to the first system, and for issuing clock restart commands to the clock control means at the end of each such transfer thereby enabling the first system to respond to the transferred signals.

A method for maintaining deterministic behavior in a first system whose operations are synchronized to clock cycles of a first clock, where the first system is forced to respond within a predefined number of clock cycles to behavior-changing commands supplied by a second system and where operations of the second system are not synchronized to the clock cycles of the first clock, the method comprising the steps of:

• blocking the second system from sending behavior-changing commands to the first system until the occurrence of a prespecified clock cycle of the first clock;
• halting the first clock at the beginning of the prespecified clock cycle;
• signalling the second system of the occurrence of said clock halting step;
• sending behavior-changing commands from the second system to the first system while the first clock is halted at the beginning of the prespecified clock cycle;
• and
• restarting the first clock after said sending step.

An apparatus for maintaining deterministic behavior in a first system, where operations of the first system are synchronized to clock cycles of a first clock, where the first system responds to behavior-changing commands supplied by a second system within a predefined number of clock cycles or predefined amount of time after such commands are received and where operations of the second system are not synchronized to the clock cycles of the first clock, said apparatus comprising:

• blocking means for blocking the second system from sending behavior-changing commands to the first system until the occurrence of a prespecified clock cycle of the first clock;
• halting means for halting the first clock at the beginning of the prespecified clock cycle;
• signalling means for signalling the second system of the occurrence of said clock halting function;
• sending means for sending behavior-changing commands from the second system to the first system while the first clock is halted at the beginning of the prespecified clock cycle;
• and
• restarting means for restarting the first clock after said sending function.

A de-glitching circuit for use in coupling a first synchronous system to a second system where the second system is not synchronous with the first system, said de-glitching circuit comprising:

• a K input terminal for receiving system clock pulses of the first system, each of said pulses including a transition-inducing edge which induces transitions in one or more signals within the first system;
• a D input terminal for receiving a data signal from within the first system, said data signal being subject to contamination by noise spikes which align with the transition-inducing edges of the system clock pulses;
• a Q output terminal for outputting a spike-free version of the received data signal;
• signal transferring means, for transferring a signal level present at the D input terminal to the Q output terminal only at the time of the transition-inducing edges of the system clock pulses, the signal transferring means having an enable input for selectively enabling or disabling such transfer;
• and
• spike-transfer suppressing means, coupled to the enable input of the signal transferring means, for disabling the transfer function of the signal transferring means if the signal levels present at the D and Q terminals are not different prior to the time of a transition-inducing edge.