Method and apparatus for performing a read-write-modify operation in a VGA compatible controller
AssigneeChips and Technologies, Inc.
InventorDhimant Bhayani
Life of this patent
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Abstract
A VGA controller with a read-modify-write cycle implemented therein is provided. By implementing the read-modify-write cycle in hardware, and by reducing the data for such operations to a single address source, read-modify-write operations can be performed in a single cycle, as opposed to separate read and write cycles, with a consequent improvement in overall operating speed.
Claims5
In the operation of a video graphics array controller having a memory and a timing sequencer, said video graphics array controller being coupled to a CPU, a method for implementing a read-modify-write cycle comprising the steps of:
- enabling the read-modify-write cycle by setting a read-modify-write control bit for said sequencer;
- specifying a particular logical operation;
- said CPU generating a hardware request for a write operation to the video graphics array memory, said hardware request specifying a first operand value, and a video graphics array memory write address;
- said sequencer generating timing signals for a read-modify-write cycle when said control bit is set;
- reading a second operand value from the video graphics array memory write address;
- performing the particular logic operation on the first operand value and the second operand value to produce a result;
- and
- writing the result of performing the particular logic operation to the video graphics array memory write address, wherein said reading, performing, and writing steps all take place during said read-modify-write cycle.
An apparatus for performing a read-modify-write cycle in a video graphics array controller having a memory, said video graphics array controller being coupled to a CPU, the apparatus comprising:
- a timing sequencer coupled to said CPU;
- means for specifying a particular logical operation
- means for enabling the read-modify-write cycle by setting a read-modify-write control bit for said sequencer;
- means, coupled to said CPU, for receiving from said CPU a hardware request for a write operation to the video graphics array memory, said hardware request specifying a first operand value, and a video graphics array memory write address, said sequencer generating read-modify-write timing signals for a read-modify-write cycle when said control bit is set;
- means responsive to the read-modify-write timing signals and to said hardware request for reading a second operand value from the video graphics array memory write address during the read-modify-write cycle;
- means for performing the particular logic operation on the first operand value and the second operand value to produce a result during said read-modify-write cycle;
- and
- means for writing the result of performing the particular logic operation to the video graphics array memory write address during said read-modify-write cycle.
Dependencies are inferred from the claim text.