System and method for serialization control of accesses to a common main storage

A serialization control system for controlling a main storage unit access in a tightly-coupled multi-processor system, said serialization control system comprising:

• a plurality of central processing units (CPUs);
• a main storage unit commonly shared by said plurality of CPUs;
• a memory control unit operatively connected to each of said plurality of CPUs;
• a plurality of caches of high speed and small capacity in said plurality of CPUs forming a hierarchical memory apparatus together with said main storage unit;
• and
• a control means for notifying an occurrence of a serialization in one of said plurality of CPUs to all other of said plurality of CPUs before the one CPU requests of said memory control unit for a serialization of main storage unit accesses and for allowing the one CPU to delay a main storage unit access which follows the occurrence of the serialization only when one of the other CPUs performs a serialization prior to the one CPU.

A serialization control system for controlling a main storage unit access in a tightly-coupled multi-processor system, said serialization control system comprising;

• a plurality of central processing units (CPUs);
• a main storage unit commonly shared by said plurality of CPUs;
• a memory control unit operatively connected to each of said plurality of CPUs;
• a plurality of caches of high speed and small capacity in said plurality of CPUs forming a hierarchical memory apparatus together with said main storage unit;
• and
• a control means for notifying an occurrence of a serialization in one of said plurality of CPUs to all other of said plurality of CPUs before the one CPU requests of said memory control unit for a serialization of main storage unit accesses and for allowing the one CPU to delay a main storage unit access which follows the occurrence of the serialization when the one CPU is notified of an occurrence of a serialization in one of the other CPUs prior to the occurrence of the serialization in the one CPU until the preceding serialization completes.

A serialization control system for controlling a main storage unit access in an information processing apparatus, said serialization control system comprising:

• a plurality of central processing units (CPUs);
• a main storage unit commonly shared by said plurality of CPUs;
• a memory control unit operatively connected to each of said plurality of CPUs;
• a plurality of caches of high speed and small capacity in said plurality of CPUs forming a hierarchical memory apparatus together with said main storage unit;
• a means for notifying an occurrence of a serialization in one of said plurality of CPUs to all other of said CPUs before the one CPU requests of said memory control unit for a serialization of main storage unit accesses;
• and
• a means for allowing the one CPU to immediately access said main storage unit whether the one CPU is notified of an occurrence of a serialization in the other CPUs or not.

A serialization control method for controlling a main storage access in an information processing apparatus comprising a plurality of a main storage apparatus commonly shared by said plurality of CPUs and

• a memory control unit operatively connected to each of said plurality of CPUs;
• said serialization control method comprising the steps of:
• (a) detecting an occurrence of a serialization in a particular CPU;
• (b) notifying the occurrence of the serialization in said particular CPU to all other of said plurality of CPUs before the particular CPU requests of said memory control unit for a serialization of main storage apparatus accesses;
• (c) examining whether the particular CPU is notified of an occurrence of a serialization in the other CPUs;
• (d) delaying a main storage apparatus access by the particular CPU which follows the occurrence of the serialization in the particular CPU when an occurrence of a serialization in the other CPUs is notified;
• and
• (e) executing said main storage unit access by the particular CPU when the other CPUs are notified of the occurrence of the serialization in the particular CPU or a serialization by the other CPUs is completed.