Apparatus and method for controlling memory requests in an information processor
AssigneeNEC Corporation
InventorKatsumi Tanaka
Life of this patent
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Abstract
An apparatus and method for controlling memory requests in an information processor is capable of generating an effective address for a first operand and a second operand, both of which are part of an instruction used to transfer data from a first memory location to a second memory location. The first operand indicates the first memory location and the second operand indicates the second memory location. By changing, in response to address overlap of the first and second operands, control of requests for memory accessing by changing the read address of a control memory, useless memory accessing is avoided resulting in faster processing.
Claims12
A pipeline-controlled information processing apparatus for generating an effective address for a first operand indicating a first memory location and a second operand indicating a second memory location, and changing control of requests for memory accessing based on an overlap between said first and second operands, comprising:
- identity detecting means for detecting and providing an indication of whether or not a first register number corresponding to a first memory address for said first operand is identical to a second register number corresponding to a second memory address for said operand;
- difference detecting means coupled to said identity detecting means for detecting a difference in displacement between said first and second operands;
- and
- changing means coupled to said difference detecting means for changing a read address of a control memory in accordance with the result of detection by said difference detecting means whenever said indication provided by said identity detecting means is that said first and second register numbers are identical.
An apparatus for controlling data transfer from a first memory location indicated by a first memory address to a second memory location indicated by a second memory address comprising:
- control memory means for storing control information corresponding to said data transfer;
- identity indicating means coupled to said control memory means for providing an indication of whether or not a first register number is identical to a second register number, said first register number corresponding to said first memory address, said second register number corresponding to said second memory address;
- difference detecting means coupled to said identity indicating means for detecting a difference in displacement between said first and second memory addresses;
- and
- read address determining means coupled to said difference detecting means for determining a read address in accordance with said difference whenever said identity indicating means provides said indication that said first register number is identical to said second register number, wherein said read address indicates a location of said control information in said control memory means.
A method for controlling data transfer from a first memory location indicated by a first memory address to a second memory location indicated by a second memory address comprising the steps of:
- storing control information corresponding to said data transfer in a control memory unit;
- indicating whether or not a first register number is identical to a second register number, said first register number corresponding to said first memory address, said second register number corresponding to said second memory address;
- detecting a difference in displacement between said first and second memory addresses;
- and
- determining a read address in accordance with said difference whenever said indicating step indicates that said first register number is identical to said second register number, wherein said read address indicates a location of said control information in said control memory unit.
Dependencies are inferred from the claim text.