Microprocessor with pipeline system having exception processing features

In a processor of the type having a pipeline formed by a plurality of consecutive processing stages, each stage having an input means for receiving an input code, a processing means for processing the input code, and an output means for providing an output code to a subsequent processing stage, a method for processing an exception, comprising the steps of:

• conveying information pertaining to an exception occurring at a given stage from the processing means of said given stage to an exception code generating means coupled thereto;
• generating an exception code at said given stage via said exception code generating means to signal occurrence of the exception, a kind of exception, and identification of said given stage;
• combining said exception code with output from the processing means to form an exception processing code;
• transferring said exception processing code to succeeding stages until said exception processing code is transferred to a special stage;
• suspending further processing at said given stage after said exception processing code is generated and transferred until an initiation of exception processing;
• decoding said exception processing code at said special stage to identify a particular exception processing sequence specific to the exception and said given stage;
• and
• initiating, at said special stage, said particular processing sequence when said exception processing code is decoded at said special stage.

In a processor of the type having a pipeline formed by a plurality of consecutive processing stages, each stage having an input means for receiving an input code, a processing means for processing the input code, and an output means for providing an output code to a subsequent processing stage, a method for processing an exception, comprising the steps of:

• storing information in means for storing coupled to said pipeline to provide stored information;
• conveying information pertaining to an exception occurring at a given stage from the processing means of said given stage to an exception code generating means coupled thereto;
• generating an exception code at said given stage via said exception code generating means to indicate occurrence of the exception at said given stage;
• transferring said exception code to succeeding stages until said exception code is transferred to a special stage;
• suspending further processing at said given stage after said exception code is generated and transferred until an initiation of exception processing sequence;
• decoding said exception code at said special stage;
• and
• initiating, at said special stage, an exception processing sequence by said pipeline using said stored information when said exception code is decoded at said special stage.

A processor having exception processing features comprising:

• a pipeline formed by a plurality of consecutive processing stages, each processing stage generating a processing code;
• generating means, coupled to each stage of said plurality of consecutive processing stages, for generating an exception processing code at a given stage to indicate the occurrence of an exception at said given stage;
• transferring means, coupled to each stage of said plurality of consecutive processing stages, for transferring said exception processing code to succeeding stages until said exception processing code is transferred to a special stage;
• suspending means, coupled to each stage of said plurality of consecutive processing stages, for suspending further processing at said given stage after said exception processing code is generated and transferred until an initiation of an exception processing sequence;
• means, coupled to said special stage, for decoding said exception processing code at said special stage;
• and
• means, coupled to said decoding means and said special stage, for executing said exception processing sequence in response to said decoded exception processing code.

In a processor having a pipeline including a plurality of successive processing stages, each processing stage comprising:

• receiving means, coupled to each stage of the plurality of successive processing stages, for receiving information from a previous processing stage;
• generating means, coupled to each stage of the plurality of successive processing stages, for generating an exception processing code upon the occurrence of an exception at said processing stage;
• transferring means, coupled to each stage of the plurality of successive processing stages, for transferring an exception processing code from said processing stage to a subsequent stage;
• and
• suspending means, coupled to each stage of the plurality of successive processing stages, for suspending processing at said stage after an exception processing code is generated at said stage and transferred to said subsequent stage until an exception processing sequence is initiated at a special stage in response to said special stage decoding said exception processing code.

A processor, comprising:

• a pipeline formed by a plurality of successive pipelined stages, with particular stages identifying a condition which initiates an exception of an exception processing sequence by a special stage of the plurality of pipelined stages, the special stage comprising:
• means for receiving an exception processing code from one of said plurality of successive pipelined stages generating said exception processing code upon occurrence of an exception at said one of said plurality of successive pipelined stages;
• means, coupled to said receiving means, for decoding said exception processing code, said decoding means including
• a first plurality of inverters for receiving said exception processing code from said receiving means;
• a second plurality of inverters each coupled to the output of one of said first plurality of inverters;
• a plurality of NAND gates coupled to the output of said first and second plurality of inverters, said inverters and NAND gates coupled in a configuration such that only one of said NAND gates is negated for each unique exception processing code received by said decoding means;
• and
• a plurality of output D flip-flops each coupled to a unique NAND gate for indicating the occurrence of said unique exception when said one NAND gate is negated;
• and
• means, coupled to said decoding means for directing control signals to specific pipelined stages in response to said decoded exception processing code.

A processor, comprising:

• a pipeline formed by a plurality of successive pipelined stages, with particular stages identifying a condition which initiates an execution of an exception processing sequence by a special stage of the plurality of pipelined stages, the special stage comprising:
• means for generating an exception processing code when an exception occurs at said special stage;
• means for receiving said exception processing code from one of said plurality of successive pipelined stages generating said exception processing code upon occurrence of an exception at said one of said plurality of successive pipelined stages;
• means, coupled to said receiving means and said generating means, for decoding said exception processing code;
• and
• means, coupled to said decoding means for directing control signals to specific pipelined stages in response to said decoded exception processing code.

A processor, comprising:

• a pipeline having at least two special stages with exception processing features, said special stages being located in said pipeline so to optimize exception processing time, and a plurality of successive processing stages, each processing stage of said plurality of successive processing stages being capable of performing normal pipeline processing and identifying a condition initiating an exception processing by one of said at least two special stages, said each processing stage including:
• means for receiving exception information from one of said plurality of successive processing stages generating said exception information, upon occurrence of an exception at said one of said plurality of successive processing stages, at a given stage;
• means, coupled to said receiving means of said given stage, for transferring said exception information to a succeeding stage;
• and
• means, coupled to said receiving means of said given stage, for suspending normal pipeline processing at said given stage after said given stage receives exception processing information and after said given stage transfers said exception information to said succeeding stage, with said given stage suspended until initiation of said exception processing at one of said at least two special stages, responsive to said exception information and disposed nearest said given stage in a downstream direction.

A method for processing an exception generated at a given stage of a plurality of pipelined processing stages capable of performing normal pipeline processing, comprising the steps of:

• generating an exception processing code at the given stage;
• transferring said exception processing code to each of a series of subsequent stages of the plurality of processing stages until said exception processing code is transferred to a special stage;
• suspending normal pipeline processing at said given stage, and each succeeding stage, after transfer of said exception processing code until said exception processing code is transferred to and processed by said special stage;
• decoding said exception processing code at said special stage after said exception processing code is received at said special stage;
• and
• directing, from said special stage, control signals to specific pipelined processing stages in response to said decided exception processing code.

An apparatus for processing an exception generated in a pipelined processor, comprising:

• a series of pipelined processing stages transferring a series of step codes, said series of stages including a given stage, a previous stage and a subsequent stage, each comprising:
• an input latch for receiving an input step code from a preceding stage;
• an output latch for providing an output code to a following stage;
• an exception code generating circuit for producing a stage specific exception step code from said input step code;
• and
• a processing unit for producing a stage specific step code from said input step code as said output code if an exception is not generated during processing, otherwise, said generating circuit providing said stage specific exception step code as said output code if an exception is generated;
• said series of stages terminating in a special stage;
• means, coupled to said series of stages, for transferring said output code from said given stage to said subsequent stage until said stage specific exception step code is received at said special stage;
• means, coupled to said series of stages, for receiving at said stage said input code from said previous stage;
• means, coupled to said series of stages, for suspending processing by said given stage after said transfer of said exception step code to said subsequent stage;
• and
• said special stage receiving said exception step code including means for initiating exception processing in response to said exception step code.

An apparatus for enabling the generation of an exception code in a pipelined processor, comprising:

• a series of pipelined processing stages transferring a series of step codes, said series of pipelined processing stages including a given stage, a previous stage and a subsequent stage, each comprising:
• an input latch for receipt of an input step code from a preceding stage;
• an output latch for holding an output step code for a following stage;
• an exception code generating circuit an exception processing code;
• means for determining if an exception is generated;
• and
• a processing unit, coupled to said input latch, said output latch, said generating circuit, and said determining means, for fetching said input step code from said preceding stage, said processing unit producing a stage specific step code from said fetched input step code and outputting said produced step code to a subsequent stage if an exception is not generated otherwise said processing unit providing information from said input step code to said generating circuit for production of said exception code which identifies the exception and a specific stage in which it was generated, said generating circuit providing its output as said stage specific step code to said output latch, and said processing unit suspending operation of said input latch when said exception is generated.

An apparatus for processing an exception generated in a pipeline processor, comprising:

• a series of pipelined processing stages terminating in a special stage for transferring a series of step codes, each processing stage comprising:
• input means for receiving an input step code from a preceding stage;
• output means for providing an output code as an input step code to an input means of a subsequent stage;
• an exception code generation circuit for providing a stage specific exception code from input information;
• means for determining if an exception is generated;
• and
• a processing unit, coupled to said input means, said output means, said exception code generation circuit, and said determining means, for producing a stage specific step code as said output code from said input step code if an exception is not generated from said input step code, otherwise, providing said input information to said exception code generation circuit for generation of said stage specific exception code and substituting said stage specific exception code as said output code if said exception is generated, said processing unit inhibiting operation of said input means if said exception is generated by suspending further processing until exception processing is initiated;
• wherein said processing unit of said subsequent stage passes a stage specific exception code received from said preceding stage to a following stage until said stage specific exception code is provided to said special stage;
• and
• said special stage decodes said input step code and initiates the pipelined processor to execute an exception processing sequence after said stage specific exception code is decoded at said special stage, wherein said exception processing sequence includes resuming operation of the suspended stages.

In a processor having a pipeline formed by a plurality of successive pipelined stages, a stage for initiating an execution of exception processing sequence, comprising:

• means for receiving exception information from one of said plurality of successive pipelined stages generating said exception information upon occurrence of an exception at said one of said plurality of successive pipelined stages;
• means coupled to said receiving means, for decoding said exception information, said decoding means comprising:
• a first plurality of inverters for receiving said exception processing code from said receiving means;
• a second plurality of inverters each coupled to an output of one of said first plurality of inverters;
• a plurality of NAND gates coupled to an output of said first and second plurality of inverters, said inverters and NAND gates coupled in a configuration such that only one of said NAND gates is negated for each unique exception processing code received by said decoding means;
• and a plurality of output D flip-flops each coupled to a unique NAND gate for indicating an occurrence of said unique exception processing code when said one NAND gate is negated;
• and
• means, coupled to said decoding means and the stage, for initiating execution of exception processing in response to said decoded exception information.