Multiprocessor system with power-on reset function
AssigneeFujitsu Limited
InventorKazuhiko Kuranaga
Life of this patent
Estimating the term…
Abstract
A multiprocessor system with power-on reset, comprising a plurality of printed circuit boards each provided with at least one processor, is provided. A power supply voltage monitor circuit is mounted on at least one of the printed circuit boards to provide a reset signal by detecting change of voltage when a power supply is energized. A first signal line serially connects the power supply voltage monitor circuit to all printed circuit boards, and a second signal line returning from the last printed circuit board may be provided, the processors having reset signal lines connected to the second signal line.
Claims20
A multiprocessor system with power-on reset, comprising:
- a plurality of printed circuit boards;
- a plurality of processors respectively provided on said plurality of printed circuit boards, each circuit board having a respective, individual processor thereon;
- power supply voltage monitor means, connectable to receive a power supply voltage, for detecting the power supply voltage and for producing a corresponding reset signal in response thereto;
- a first signal line connecting said power supply voltage monitor means and at least two of said printed circuit boards;
- and
- a reset signal line provided in parallel with the first signal line and connecting at least two of said printed circuit boards.
A multiprocessor system with power-on reset, comprising:
- a plurality of printed circuit boards, at least one of said printed circuit boards connectable to receive a system power source voltage;
- a plurality of processors, at least one processor provided on each of said printed circuit boards;
- a connector having two parallel lines to connect at least two of said printed circuit boards;
- and
- power supply voltage monitor means, provided on one of said printed circuit boards, for resetting said processors by supplying a reset signal to said printed circuit boards through one of said lines of said connector and for returning the reset signal to the one of said printed circuit boards through the other of said lines of said connector.
A multiprocessor system with power-on reset, comprising:
- a plurality of printed circuit boards;
- a plurality of processors, at least one processor provided on each of said printed circuit boards;
- a reset signal line connecting at least two of said printed circuit boards;
- first power supply voltage monitor means, provided on one of said printed circuit boards, for detecting a power supply voltage and for providing a first reset signal responsive to the detecting;
- and
- second power supply voltage monitor means, provided on another of said printed circuit boards, for receiving the first reset signal and for providing a second reset signal over said reset signal line to reset said processors, the second reset signal provided responsive to receiving the first reset signal.
A multiprocessor system with power-on reset, comprising:
- a plurality of printed circuit boards;
- a plurality of processors, at least one processor provided on each of said printed circuit boards;
- first power supply voltage means, connectable to receive a power supply voltage and provided on one of said printed circuit boards, for providing a reset signal by detecting the power supply voltage;
- a first signal line connecting said first power supply voltage means to at least one of said processors located on all other of said printed circuit boards;
- and
- a second signal line provided in parallel with the first signal line and connecting said processors located on the all other of said printed circuit boards to the at least one processor provided on the one of said printed circuit boards.
A multiprocessor system with power on reset, comprising:
- a master printed circuit board, including:
- master power supply monitoring means for detecting a power supply voltage, for receiving a first reset signal and for providing a second reset signal responsive to receipt of the first reset signal and detection of the power supply voltage,
- delay means for delaying the second reset signal and for providing a third reset signal responsive to the second reset signal after the delaying, and
- a master processor operatively connected to said delay means;
- a slave printed circuit board, including:
- slave power supply monitoring means for detecting the power supply voltage and for providing the first reset signal responsive to detection of the power supply voltage,
- a slave processor operatively connected to said delay means, the third reset signal resetting said master processor and said slave processor simultaneously.
Dependencies are inferred from the claim text.