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US 5,297,260 AGranted
Processor having a plurality of CPUS with one CPU being normally connected to common bus
AssigneeHitachi, Ltd.
InventorMasatsugu Kametani
Life of this patent
Estimating the term…
Abstract
A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a dual-port RAM accessible from said CPUs, and a common bus switch circuit for connecting any one of said CPUs to a common bus shared by said CPUs.
Claims18
A processor module comprising:
- a common bus for transferring first and second information;
- a first CPU providing an always active bus request signal so as to be normally connected to said common bus for processing the first information from said common bus to generate first data from the first information;
- a second CPU for processing the second information from said common bus to generate second data from the second information, for generating an access request signal requesting connection of said second CPU to said common bus, and for terminating the access request signal upon termination of the requirement of said second CPU for access to said common bus;
- first and second local buses connected respectively to said first and second CPUs, for transferring the first and second information, respectively;
- said first CPU being responsive to the access request signal from said second CPU for providing a disconnect acknowledge signal;
- and
- a controller for normally connecting the first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto.
4 more elements
A processor system comprising:
- a plurality of processors, each processor including:
- (a) a common bus for transferring first and second information;
- (b) a first CPU providing an always active bus request signal so as to be normally connected to said common bus, for processing the first information from said common bus to generate first data from the first information, and selectively generating a first system bus access request signal while processing the first information,
- (c) a second CPU for processing the second information from said common bus to generate second data from the second information, for generating a common bus access request signal upon requirement of said second CPU for access to said common bus, for terminating the common bus access request signal after termination of processing by said second CPU using said common bus, and for selectively generating a second system bus access request signal while processing the second information,
- (d) a memory for storing the first and second data from said first and second CPUs for application to said first and second CPUs,
- (e) first and second local buses connected respectively to said first and second CPUs, for transferring the first and second information, respectively,
- (f) said first CPU being responsive to the access request signal from the second CPU for providing a disconnect acknowledge signal, and
- (g) a controller for normally connecting said first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto;
- a system bus connected to said plurality of processors;
- and
- a system switch for connecting said system bus to the common bus of a selected one of said plurality of processors in response to a system bus access request signal from said selected processor.
8 more elements
A processor system for controlling an object comprising:
- a plurality of processors, each processor including:
- (a) a common bus for transferring first and second information;
- (b) a first CPU providing an always active bus request signal so as to be normally connected to said common bus, for processing the first information to control a portion of the object based on a control algorithm predetermined for the object, and selectively generating a first system bus access request signal and instructions while processing the first information,
- (c) a second CPU for processing the second information to supply instructions to said first CPU and to manage said first CPU to cause said second CPU to perform backup of said first CPU, for generating a common bus access request signal upon requirement of said second CPU for access to said common bus, for terminating the common bus access request signal after termination of processing by said second CPU using said common bus, and for selectively generating another first system bus access request signal and instructions while processing the second information,
- (d) a memory for storing the first and second data respectively obtained from processing by said first and second CPUs in response to the instructions from said first and second CPUs,
- (e) first and second local buses connected to first and second CPUs, respectively, for transferring the first and second information, respectively,
- (f) said first CPU being responsive to the access request signal from the second CPU for providing a disconnect acknowledge signal, and
- (g) a controller for normally connecting said first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto;
- a system bus connected to said plurality of processors;
- and
- a first system switch responsive to a first system bus access request signal from one of said processors to connect said first system bus to the common bus of said one of said processors.
8 more elements
Dependencies are inferred from the claim text.