Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism

A parallel computer constructed of a plurality of processor elements and a network for connecting said plurality of processor elements for transfer of data therebetween, comprising:

• a local memory provided in each processor element and including a plurality of data regions which include a group of receive data regions holding a number of data received from other processor elements;
• a plurality of tag regions each provided for a corresponding one of the group of receive data regions of said local memory within said each processor element, each of said tag regions holding a tag representing whether data held by a corresponding one receive data region is valid or invalid;
• means provided in said each processor element for transmitting data to another destination processor element via the network, in response to a send request from a program being executed by said each processor element, the program being programmed so as to issue the send request without receiving a request for transmission of the data, from a program being executed by the destination processor;
• writing means provided in said each processor element for receiving data transmitted from another processor elment via the network;
• means provided in said each processor element for writing the received data into one receive data region among the group of receive data regions provided in said each processor element;
• means provided in said each processor element for setting, in a tag region corresponding to said one receive data region, a tag representative that a content of the one receive data region is valid, when the received data is written into the one receive data region;
• and,
• access means provided in said each processor element and responsive to a read request which has been issued from the program being executed by said each processor element and which requests reading of received data from one of the group of receive data regions for checking if one tag held within one of said tag regions provided in correspondence to said one receive data region indicates validity, and for repeating the checking, if the one tag indicates invalidity initially, until said one tag indicates validity.

A parallel computer comprising:

• a plurality of processor elements;
• a network for connecting said plurality of processor elements;
• each processor element including:
• a local memory for holding one of programs to be executed in parallel by said processor elements and data to be used by the program;
• means for executing instructions of the program;
• means for transmitting data to a destination processor element via the network in response to a send instruction within the program, the program being programmed so as to execute the instruction without receiving a request for transmission of the data from the destination processor element;
• means for receiving from the network data sent from another processor element;
• a receive memory including a group of data regions each prepared for holding data received from another processor element and a plurality of tag regions each provided for a corresponding one of the group of data regions, each of said tag regions being prepared for holding a tag representative of whether data held in a corresponding data region is valid or invalid;
• writing means for writing data received by said means for receiving into one of the group of data regions;
• means for setting in one of the tag regions corresponding to the one data region to a tag representative of validity when the received data is written into the one data region of said receive memory by said writing means;
• and,
• access means responsive to a receive instruction of the program, which requests read out of received data from one of the group of data regions designated by the receive instruction, the access means including,
• means for checking if a tag stored in one tag region corresponding to said one data region indicates validity,
• means for repeating the checking until said one tag represents validity in case the one tag represents invalidity initially, and
• means for supplying data held in said one data region under a condition that the one tag indicates validity.

A parallel computer comprising:

• (a) a plurality of processor elements each for executing one of programs to be executed in parallel by said processor elements, and
• (b) a network for transferring data between said plurality of processor elements,
• (c) each of said processor elements including:
• (c1) a local memory for holding one of the programs and data used by the program;
• (c2) a group of data regions each for holding data sent from another processor element;
• (c3) a group of tag regions each provided in correspondence to one of the group of data regions and each prepared for holding a tag indicative of validity of data held in a corresponding one of the group of data regions;
• (c4) means for executing instructions of the program;
• (c5) means responsive to execution by said executing means, of a send instruction which requires transmission of one data which belongs to a group of data to a destination processor element for generating an address of one of the group of data regions within the destination processor element, into which the one data is to be written, based upon a main identifier and a sub-identifier designated by the send instruction,
• the main identifier being predetermined for the data group and the sub-identifier being predetermined for the one data;
• the program being programmed so as to execute the send instruction without receiving a request for transmission of the one data from the destination processor element;
• (c6) means responsive to the send instruction for transmitting to said network a message containing the data and the generated address;
• (c7) means for receiving a message sent from another processor element via the network, in parallel to execution of instructions by said executing means;
• (c8) write means for writing received data included in the received message into one of the group of data regions within said each processor element, based upon an address contained in said received message and for writing a tag which indicates validity into one of the group of tag regions corresponding to the one data region;
• and
• (c9) access means responsive to execution by said execution means, of a receive instruction which requires readout of received data, for checking if one of a number of tags held within a number of selected tag regions provided in correspondence to a number of successively located selected data regions indicates validity, the selected data regions being determined by a main identifier designated by said receive instruction, and responsive to a tag held in one of the number of selected tag regions indicating validity for reading received data from one of said number of selected data regions corresponding to the one selected tag region.

A parallel computer comprising:

• (a) a plurality of processor elements each for executing one of programs to be executed in parallel, and
• (b) a network for transferring data between said plurality of processor elements,
• (c) each of said processor elements including:
• (c1) a local memory for holding one of the programs and data used by the program;
• (c2) a group of data regions each for holding data sent from another processor element;
• (c3) a group of tag regions each provided in correspondence to one of the group of data regions and each prepared for holding a tag indicative of validity of data held in a corresponding one of the group of data regions;
• (c4) executing means for executing instructions of the program;
• (c5) means responsive to execution by said executing means, of a send instruction which requires transmission of one data which belongs to a group of data to a destination processor element for transmitting to said network a message containing the one data and a data identifier comprised of a main identifier and a sub-identifier,
• the main identifier being predetermined for the data group and the sub-identifier being predetermined for the one data,
• the program being programmed so as to execute the send instruction without receiving a request for transmission of the one data from the destination processor element;
• (c6) means for receiving a message supplied from said network, in parallel to execution of instructions by said executing means;
• (c7) means for generating an address of one of the group of data regions into which received data included in the received message is to be written, from a main identifier and a sub-identifier contained in the received message, for writing the received data into the one data region based upon said address, and for writing a tag which indicates validity into one of the group of tag regions corresponding to the one data region.
• the one data region being one determined by the sub-identifier among a number of successive data regions determined by the main identifier within the group of data regions within said each processor element;
• and
• (c8) access means responsive to execution by said executing means, of a receive instruction within the program, which requires readout of received data for checking if one of a number of tags held within a number of selected tag regions provided in correspondence to a number of successively located selected data regions indicated validity, the selected data regions being determined by a main identifier designated by said receive instruction, and responsive to a tag held in one of the number of selected tag regions indicating validity for reading received data from one of said number of selected word regions corresponding to the one selected tag region.

A parallel computer comprising:

• (a) a plurality of processor elements, and
• (b) a network for transferring data between said plurality of processor elements,
• (c) each of said processor elements including:
• (c1) a local memory for holding one of programs to be executed in parallel by said processor elements and data used by the program;
• (c2) a group of data regions each for holding data sent from another processor element;
• (c3) a group of tag regions each provided in correspondence to one of the group of data regions and each prepared for holding a tag indicative of validity of data held in a corresponding one of the group of data regions;
• (c4) executing means for executing instructions of the program;
• (c5) means responsive to execution by said executing means, of a send instruction which requires transmission of a group of sequentially ordered data elements to a destination processor element for generating, for each data element of the group, a corresponding address of a corresponding one of the group of data regions within the destination processor element, into which said each data element of the group is to be written,
• the send instruction being executed without receiving a request for transmission of the group from the destination processor element,
• the one data region being one determined by sequential order of said each data element among a number of successively located selected data regions within the group of data regions within the destination processor element,
• the selected data regions being determined by information designated by the send instruction;
• (c6) means for sequentially transmitting the group of data elements to the destination processor element via the network, each data element being transmitted together with the address generated by the address generating means for said each data element;
• (c7) means for sequentially receiving, via the network, a group of sequentially ordered data elements sent from one of the processor elements each together with an address generated for each data element;
• (c8) means for writing each data element of the received group into one of the data regions within the group of data regions, based upon the address accompanying said each data element and for writing a tag indicative of validity into one of the group of tag regions corresponding to the one data region;
• and
• (c9) access means responsive to execution by said executing means, of a receive instruction which requires receipt of a group of data elements for sequentially reading the required group of data elements from a number of successively located selected data regions within the group of data regions, said access means including,
• means for determining addresses of the number of selected data regions in response to information designated by the receive instruction, and
• means for checking if each of a number of selected tag regions within the group of tag regions, corresponding to each of the number of selected data regions holds a tag indicative of validity before data held in said each selected data region is read out.

A method for inter-processor communication of data in a parallel computer which comprises a plurality of processors each of which including a local memory for holding one of programs to be executed in parallel and data related to the program, a group of reception data areas each for holding data received from another processor via the network and a group of tag areas each provided in correspondence to one of the reception data areas and each for holding a tag which indicates whether or not data held in a corresponding reception data area is valid, the method comprising steps executed by each processor element, the steps including:

• transmitting to a destination processor element, data and information related to an address of one of the group of reception data areas within said destination processor element into which the data is to be written, in response to a send request issued by a program being executed by said each processor element, the program being programmed so as to issue the send request without receiving a request from the destination processor element for transmission of the data;
• receiving data and information related to an address both transmitted from another processor element, the receiving being done in parallel to execution of instructions of the program by said each processor element;
• writing the received data into one of the group of reception data areas, in response to the received address related information;
• writing a tag which indicates validity into one of the group of tag regions corresponding to said one reception data area;
• checking if a tag held in one of the tag areas indicates validity, in response to a receive request issued by the program, the one tag region corresponding to one of the reception data areas designated by the receive request;
• repeating the checking until the tag indicates validity, in case the tag indicates invalidity initially;
• and
• supplying data held in said one reception data areas as valid data for processing by the destination processor, under a condition that the tag has been found as one indicating validity.