Pattern detection and synchronization circuit

An apparatus for recovering data from a plesiosynchronous binary bit stream, each bit being a one or a zero, said stream containing at least encoded data and sequences of a preamble pattern interleaved with said data, wherein said preamble pattern has a given ratio R of ones to zeroes when averaged over at least n bits, and a length of at least m bits, where m and n are integers and R is a ratio of two integers, and m>n;

• and said data are encoded according to a code producing a probability P that the ratio of ones to zeroes in the coded data differs from said given ratio R when averaged over at least n bits, and a ratio of ones to zeroes different from said given ratio R when averaged over at least n+k bits, where k is an integer, and k>0, comprising:
• a variable frequency clock,
• data detector means, synchronized by said clock, for detecting said data in said bit stream, and
• means for synchronizing said clock to said bit stream,
• characterized in that said apparatus comprises:
• a preamble detection circuit, comprising means for determining the ratio r of ones to zeroes over an n bit sampling period, where r is a ratio of two integers, for detecting said preamble pattern responsive to receipt of n bits of said pattern, and
• means for disabling said means for synchronizing until said preamble detection circuit has detected said preamble pattern.

An apparatus for recovering data from a binary bit stream, each bit being a first value or a second value different from said first value, said stream containing at least data and sequences of a preamble pattern interleaved with said data, wherein said preamble pattern has a length of at least m bits, and a given ratio R of average numbers of bits of said first value to bits of said second value, where m is an integer and R is a ratio of two integers;

• and said data are coded to have a ratio of average numbers of bits of said first value to bits of said second value different from said given ratio when averaged over at least k bits, where k is an integer, comprising:
• a variable frequency clock,
• data detector means, synchronized by said clock, for detecting said data in said bit stream, and
• means for synchronizing said clock to said bit stream,
• characterized in that said apparatus comprises:
• a preamble detection circuit, for detecting reception of said preamble pattern responsive to receipt of n bits of said pattern, where n is an integer, and n<m;
• n.ltoreq.k;
• and said circuit comprises means for determining the ratio of average numbers of bits of said first value to bits of said second value over an n bit sampling period, and
• means for disabling said means for synchronizing until said preamble detection circuit has detected said preamble pattern.

An apparatus for recovering data from a binary bit stream, each bit being a first value or a second value different from said first value, said stream containing at least data and sequences of a preamble pattern interleaved with said data, wherein said preamble pattern has a length of at least m bits, and a given ratio R of average numbers of bits of said first value to bits of said second value, where m is an integer and R is a ratio of two integers;

• and said data are coded to have a probability P that the ratio of bits of said first value to bits of said second value in the coded data differ from said given ratio when averaged over at least k bits, where k is an integer, comprising:
• a variable frequency clock,
• data detector means, synchronized by said clock, for detecting said data in said bit stream, and
• means for synchronizing said clock to said bit stream,
• characterized in that said apparatus comprises:
• a preamble detection circuit, for detecting reception of said preamble pattern responsive to receipt of n bits of said pattern, where n is an integer, an n<m;
• n<k+1, and
• means for disabling said means for synchronizing until said preamble detection circuit has detected said preamble pattern,
• and wherein said preamble detection circuit comprises means for determining the ratio r of bits of said first value to bits of said second value over an n bit sampling period, where r is a ratio of two integers, and, responsive to determination that said ratio r over said n bit period equals said given ratio R, providing to said means for disabling a signal that said preamble pattern is detected,
• said preamble detection circuit continues determining said ratio r for an additional period of time, and
• said apparatus further comprises means for disabling said means for synchronizing responsive to determination during said additional period that said ratio r is not substantially equal to said given ratio R.