Method and apparatus for providing a digital audio interface protocol

A circuit for asynchronous communication of digital data at a plurality of data rates, comprising;

• a digital transmitter coupled to a transmission means, said digital transmitter transmitting a series of data frames, each of said data frames comprised of said digital data and a sync pattern;
• a digital receiver coupled to said transmission means, said digital receiver capable of locating said sync pattern within each of said data frames based upon an output of an oscillator;
• a counting means for counting a number of oscillator periods;
• said oscillator executing a first adjustment of its frequency until the number of oscillator periods counted during said sync pattern is within a first stage range, allowing said digital receiver to recognize said sync pattern.
• said oscillator executing a second adjustment of its frequency until the number of oscillator periods occurring in one dataframe is within a second stage range, making said oscillator capable of being phaselocked to the transmitted dataframes.
• phase locking means to lock said oscillator to said transmitted data frames.

A method for phase locking an oscillator to the transmit frequency of a series of data frames, each data frame comprising N bits of binary data, each data frame further comprised of a sync pattern and a plurality of digitally sampled bits, said sync pattern comprised of a plurality of consecutive identical binary bits terminated by a single termination bit, said method comprising the steps of:

• (a) transmitting said series of data frames from a digital transmitter to a digital receiver;
• (b) locating said sync pattern in each data frame;
• (c) interpreting said sync pattern using a counter based on an output signal of an oscillator having a frequency;
• (d) increasing said frequency of said oscillator if said sync pattern is interpreted as having less than a first lower limit of consecutive identical binary bits;
• (e) decreasing said frequency of said oscillator if said sync pattern is interpreted as having more than a first upper limit of consecutive identical binary bits;
• (f) repeating steps (b) through (e) until no frequency adjustment of said oscillator is required in step (d) or step (e);
• (g) counting a number of oscillations of said oscillator between consecutive occurrences of said sync pattern;
• (h) increasing said frequency of said oscillator if said number of oscillations of said oscillator is less than a second lower limit;
• (i) decreasing said frequency of said oscillator if said number of oscillations of said oscillator is more than second upper limit;
• (j) repeating steps (g) through (i) until no frequency adjustment of said oscillator is required in step (h) or step (i);
• (k) comparing a phase of said oscillator with a phase of said transmit frequency of said data frames;
• (l) advancing said phase of said oscillator if said phase of said oscillator is behind said phase of said transmit frequency of said data frames;
• (m) retarding said phase of said oscillator if said phase of said oscillator is ahead of said phase of said transmit frequency of said data frames;
• (n) repeating steps (k) through (m) until no phase adjustment is required in step (l) or (m).