Digital clock dejitter circuits for regenerating clock signals with minimal jitter

Apparatus for regenerating a jittered stream of data of a first standard telecommunications signal, said apparatus having a second telecommunications clock signal as an input thereto, said second telecommunications clock signal being a fast clock signal at a substantially faster rate than the rate of said first standard telecommunications signal, comprising;

• a) FIFO means for receiving said jittered stream of data, and for providing said data for output from said apparatus;
• b) a digital, integer/fractional FIFO fullness gauge means coupled to said FIFO means for tracking the relative rates at which said FIFO means receives and outputs said data and for generating therefrom a first control indication which is responsive to an integer fullness of said FIFO means, and for generating from said first control indication and from an indication of a fractional fullness of said FIFO means, a second control indication;
• and
• c) a controllable digital frequency generator means coupled to said digital integer/fractional FIFO fullness gauge means for receiving said fast clock signal and said second control indication, and for generating therefrom a substantially jitter-free output clock signal at the same nominal rate as said first telecommunications signal, said substantially jitter-free output clock signal being coupled to said FIFO means in order to cause said FIFO means to provide said data for output from said apparatus in a substantially jitter-free manner at said nominal rate.