Doubling circuit
AssigneeNEC Corporation
InventorSatoshi Tatsumi
Life of this patent
Estimating the term…
Abstract
A doubling circuit for adjusting the duty ratio of an output signal automatically and implemented as a digital circuit. A variable delay circuit delays an input signal while an exclusive-OR (EOR) gate produces EOR of the output signal of the delay circuit and the input signal. The resulting output of the EOR gate has a frequency double the frequency of the input signal. A low pass filter (LPF) filters the output signal of the EOR gate to produce a means voltage thereof. An integrating circuit integrates a difference between the output voltage of the LPF and a reference voltage. The delay of the variable delay circuit is controlled by the output of the integrating circuit. As a result, the doubled signal from the EOR gate has the duty ratio thereof automatically adjusted.
Claims4
A doubling circuit for doubling a frequency of an input signal, comprising:
- variable delay means for delaying the input signal to produce a delayed signal;
- exclusive-OR (EOR) gate means for EORing the delayed signal from said variable delay means and the input signal to produce an EOR signal;
- low pass filter (LPF) means for filtering the EOR signal from said EOR gate means to produce a filtered signal;
- and
- integrating circuit means for integrating a voltage difference between the filtered signal from said LPF means and a reference voltage to produce an integrated signal;
- said variable delay means delaying the input signal a period of time controlled by the integrated signal from said integrating circuit means.
A method of doubling a frequency of an input signal, comprising the steps of:
- (a) delaying the input signal a predetermined period of time to produce a delayed signal;
- (b) EORing the input signal and the delayed signal to produce an EOR signal;
- (c) low-pass filtering the EOR signal to produce a filtered signal;
- and
- (d) integrating a voltage difference between the filtered signal and a reference signal, whereby the period of time by which the input signal is to be delayed is controlled.
Dependencies are inferred from the claim text.