US 5,297,173 A · Phase/frequency comparator for timing recovering circuit

Abstract

The phase/frequency comparator comprises a known phase comparator for comparing the phases of an digital input signal with a clock signal of which the period varies to within one time interval with respect to the period of the input signal. Such a phase comparator produces a first error signal whose sign, and preferably magnitude, vary as a function of the difference between the phases. The phase/frequency comparator is intended to produce a second error signal which replaces the first error signal and whose sign, and preferably magnitude, vary as a function of the difference between the periods. According to a preferred embodiment, a phase shift assessing circuit detects a predetermined phase shift, e.g. substantially equal to 0, between the clock signal and the input signal during a clock period. A sign detecting circuit detects the sign of the difference between the periods for the predetermined phase shift, and a logic circuit derives two signals having pulse widths as a function of said periods thereby deriving the second error signal by differentiation. The phase/frequency comparator is particularly intended for a phase locked loop for recovering the timing of the input signal.

Claims18

Dependent claims

A phase/frequency comparator, for comparing a digital input signal (SE) having a given binary period and a clock signal (HR) having a clock period variable to within a first time interval with respect to said given binary period, comprising:

(a) phase comparing means (CP) for comparing the respective phases of said digital input signal and said clock signal to produce a first error signal (.epsilon.2, .epsilon.4) having a sign that is a function of the sign of the phase difference between said digital input signal and said clock signal;
(b) phase shift assessing means (51, 751, 851) for producing a phase detection signal (SP) in accordance with a phase shift between said clock signal and said digital input signal that falls within at least one given phase shift range, said phase shift assessing means including:
(1) means for detecting transitions between logic states in said digital input signal, thereby to derive transition pulses having a width greater than said first time interval;
and
(2) means for deriving from said phase detection signal a pulse having a width equal to at least one clock period in response to a transition pulse substantially in phase with a clock signal complementing said clock signal;
and
(c) second error signal producing means (52, 703) operable in response to said first error signal and said phase detection signal to produce a second error signal (.epsilon.5, .epsilon.6, .epsilon.7, .epsilon.8) the sign of which is a function of the difference between said given binary period and said clock period.

4 more elements

A phase/frequency comparator, for comparing a digital input signal (SE) having a given binary period and a clock signal (HR) having a clock period variable to within a predetermined first time interval with respect to said binary period, comprising:

(a) phase comparing means (CP) for comparing the respective phases of said digital input signal and said clock signal to produce a first error signal (.SIGMA..sub.2, .SIGMA..sub.4) having a sign that is a function of the sign of the phase difference between said digital input signal and said clock signal;
(b) phase shift assessing means (51, 751, 851) for producing a phase detection signal (SP) in accordance with a phase shift between said clock signal and said digital input signal that falls within at least one given phase shift range;
and
(c) second error signal producing means (52, 703) operable in response to said first error signal and said phase detection signal to produce a second error signal (.epsilon..sub.5, .epsilon..sub.6, .epsilon..sub.7, .epsilon..sub.8) the sign of which is a function of the difference between said binary period and said clock period;
(d) said phase shift comparing means including means for deriving first and second pulses composing said first error signal, said first pulses having widths that vary as a function of a phase shift between edges of said digital input signal and corresponding edges of said clock signal, and being phase-shifted by a half of said predetermined binary period with regard to said edges of said digital input signal, and said second pulses having widths equal to a half of said clock period and being synchronous with said clock signal;
(e) said second error signal producing means including pulse width comparing means for comparing said widths of said first and second pulses in response to said phase detection signal, thereby deriving a logic sign signal of which the states are representative of the sign of the difference between said given binary period and said clock period, and means for selecting first and second pulses during at least one clock period determined by said phase detection signal, thereby deriving first and second signals, respectively, reproducing said first and second selected pulses contained in said clock period and the state of said sign signal and the opposite state of said sign signal before and after said clock period said first and second signals being applied to said differential amplification means which produces said second error signal.

3 more elements

A timing recovering circuit comprising a phase/frequency comparator, loop filtering means, and a voltage controlled oscillator combined into a phase locked loop means, said phase/frequency comparator being operable to compare a digital input signal (SE) having a given binary period and a clock signal (HR) having a clock period variable to within a predetermined first time interval with respect to said binary period, comprising:

(a) phase comparing means for comparing the respective phases of said digital input signal and said clock signal generated by said oscillator, thereby deriving a first error signal whose sign is a function of the sign of the phase difference between said digital input signal and said clock signal,
(b) means for detecting transitions between logic states in said digital input signal thereby deriving transition pulses having a width substantially equal to a second time interval greater than said first time interval,
(c) means for deriving phase detection pulses having a width equal to at least one clock period in response to ones of said transition pulses substantially in phase with a clock signal complementing said clock signal,
(d) means for reproducing at least one period of said clock signal into a reproduced period in response to each of said phase detection pulses, and
(e) means for reading the sign of said first error signal in response to said reproduced period of said clock signal thereby deriving a second error signal of which the polarity varies as a function of the sign of the difference between said predetermined binary period and said clock period, said second error signal voltage-controlling said oscillator via said filtering means.

2 more elements

(a) means for deriving a first error signal including first pulses having widths that vary as a function of a phase shift between edges of said digital input signal and following corresponding edges of a clock signal generated by said oscillator, and said first pulses being phases shifted by half of said predetermined binary period with regard to said edges of said digital input signal, and second pulses having widths proportional to said clock period;
(b) means for detecting transitions between logic states in said input signal, thereby deriving transition pulses having a width substantially equal to a second time interval that is greater than said first predetermined time interval;
(c) means for deriving phase detection pulses having a width equal to at least one clock period in response to ones of said transition pulses substantially in phase with a second clock signal that is the complement of said clock signal;
(d) pulse width comparing means for comparing said widths of said first and second pulses in response to each of said phase detection pulses, thereby to derive a logic sign signal the states of which are representative of the sign of the difference between said predetermined binary period and said clock period;
(e) means for selecting ones of said first and second pulses during at least one clock period determined by said phase detection pulses, thereby deriving first and second signals respectively reproducing said first and second selected pulses contained in said at least one clock period and the state of said sign signal and the opposite state of said sign signal before and after said at least one clock period;
and
(f) means for differentially amplifying said first and second signals, thereby deriving a second error signal voltage-controlling said oscillator via said filtering means, said second error signal having polarity that varies as a function of the sign of the difference between said predetermined binary period and said clock period.

4 more elements

A timing recovering circuit comprising a phase/frequency comparator, loop filtering means and a voltage controlled oscillator combined into a phase locked loop means, said phase/frequency comparator being operable to compare a digital input signal (SE) having a given binary period and a first clock signal (HR) having a clock period variable to within a predetermined first time interval with respect to said binary period, comprising:

(a) means for deriving a first error signal including first pulses having widths that vary as a function of a phase shift between edges of said digital input signal and following corresponding edges of a clock signal generated by said oscillator, and said first pulses being phase shifted by one half of said predetermined binary period with regard to said edges of said digital input signal, and second pulses having widths proportional to said clock period;
(b) means for detecting transitions between logic states in said input signal thereby deriving transition pulses having a width substantially equal to a second predetermined time interval more than said first predetermined time interval;
(c) means for deriving phase detection pulses having a width equal to at least one clock period in response to ones of said transition pulses substantially in phase with a second clock signal that is the complement of said first clock signal;
(d) means for deriving opposite phase pulses having a width at least equal to one clock period in response to ones of said transition pulses substantially in phase with said clock signal;
(e) means for deriving phase detection pulses substantially between said phase pulses and said opposite phase pulses;
(f) pulse width comparing means for comparing said widths of said first and second pulse in response to each of said phase detection pulses thereby deriving a logic sign signal the states of which are representative of the sign of the difference between said predetermined binary period and said clock period;
(g) means for selecting ones of said first and second pulses during at least one clock period determined by said phase detection pulses thereby deriving first and second signals respectively reproducing said first and second selected pulses contained in said at least one clock period and the state of said sign signal and the opposite state of said sign signal before and after said at least one clock period;
and
(h) means for differentially amplifying said first and second signals, thereby deriving a second error signal voltage-controlling said oscillator via said filtering means, said second error signal having a polarity that varies as a function of the sign of the difference between said binary period and said clock period.

6 more elements

Dependencies are inferred from the claim text.

Phase/frequency comparator for timing recovering circuit

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Phase/frequency comparator for timing recovering circuit

Life of this patent

Abstract

Claims18