Adjustable weighted random test pattern generator for logic circuits

An apparatus for generating test patterns, said apparatus comprising:

• a random pattern generator for generating a series of digit signals at an output of the random pattern generator, each digit signal in the series having an initial probability of having a first value, the initial probability being adjustable;
• a shift register for storing a plurality of digit signals of a test pattern, said shift register having an input for receiving digit signals from the output of the random pattern generator, said shift register having a plurality of outputs for outputting a test pattern comprising the stored digit signals;
• characterized in that the shift register comprises:
• a series of latches, each latch having an input and having an output, the input of a first latch being connected to the output of the random pattern generator, the output of each latch being connected to the input of a next adjacent latch, each latch storing one digit signal of a test pattern;
• and
• at least a first logic circuit for connecting the output of the random pattern generator to the input of the first latch or for connecting the output of a latch to the input of a next adjacent latch, said logic circuit having first and second states, and a control input for selecting either the first state or the second state, said logic circuit having a data output for outputting a series of digit signals, each digit signal output by the logic circuit having a first output probability of having the first value when the logic circuit is in the first state, the first output probability being independent of the initial probability, each digit signal output by the logic circuit having a second output probability of having the first value when the logic circuit is in the second state, the second output probability being dependent on the initial probability.