Emergency circuit for, e.g., numerical control unit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHirohiko Kazato
Life of this patent
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Abstract
A fault detection/alarm system includes an oscillator at one end of a signal cable whose clock output is OR'ed with a fault detection signal. A receiving unit receives the OR'ed signal and detects the leading edge of the clock. If the clock signal disappears due to breakage of the signal cable, the appearance of a fault detection signal or other reason, the leading edges are no longer detected, causing the raising of a fault signal which may be an emergency stop signal for the receiving unit.
Claims11
A fault detection or alarm system for use with multiple units which are connected by a signal cable, comprising:
- an oscillator provided in a first unit for generating a clock signal;
- a fault detection circuit for detecting faults in said units;
- a signal transmission circuit, directly connected to said fault detection circuit and between said oscillator and said signal cable, for transmitting said clock signal to said signal cable only while receiving an output from said fault detection circuit indicating that a fault has not been detected;
- and
- signal determination circuit means, provided in at least one second unit, for receiving transmitted signals from said signal cable and for determining that a fault has occurred based on an absence of the clock signal from said transmitted signal.
A fault detection or alarm system, comprising:
- a first unit containing detection means for generating a clock signal only when no faults are detected in said system;
- at least one second unit including determination means for receiving said clock signal and for generating a fault signal in response to an absence of said clock signal;
- and
- means for exercising control over said at least one second unit upon receipt of said fault signal,
- wherein said determination means includes an edge detection circuit for generating a pulse in response to a leading edge of each pulse in said clock signal received by said determination means, and
- wherein said determination means includes a delay circuit, coupled to said edge detection circuit, for outputting a pulse having a predetermined time constant for each pulse received from said edge detection circuit, and inverter means, coupled to said delay circuit for inverting an output from the delay circuit, said delay circuit and inverting means operating to output a signal having a first level representing a no fault condition while receiving pulses from said edge detection circuit.
Dependencies are inferred from the claim text.