US 5,297,105 AGranted

Semiconductor memory circuit

AssigneeOki Electric Industry Co., Ltd.

InventorsKatsuaki Matsui, Sampei Miyamoto, Tamihiro Ishimura

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Abstract

A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each including memory cells. First to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and the first information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated so as to select one memory cell group in the second memory cell block.

A semiconductor memory circuit for selecting one of memory cell groups in response to an address signal having block selection information, first significant bit information and second significant bit information;

comprising:
a first memory cell block having a plurality of cells;
a second memory cell block having a plurality of memory cell groups each including a plurality of memory cells;
a third memory cell block having a plurality of memory cell groups each including a plurality of memory cells;
decoder group having a plurality of first
a first decoders, said first decoders each being coupled to one of the memory cell groups in said first memory cell block;
a second decoder group having a plurality of second decoders, said second decoders each being coupled to one of the memory cell groups in said second memory cell block;
a third decoder group having a plurality of third decoders, said third decoders each being coupled to one of the memory cell groups in said third memory cell block;
a first logic circuit outputting a first common block selection signal with respect to said first and second memory cell blocks in response to the block selection information of the address signal;
a second logic circuit outputting a second common block selection signal with respect to said second and third memory cell blocks in response to the block selection information of the address signal;
a third logic circuit, in response to the second significant bit information, applying a plurality of first common decode signals to said first and second decoder groups upon the first common block selection signal being outputted;
a fourth logic circuit, in response to the first significant bit information, applying a plurality of second common decode signals to said second and third decoder groups upon the second common block selection signal being outputted;
and
one of said second decoders in said second decoder group, in response to said first and second common decode signals, being activated so as to select one of the memory cell groups in said second memory cell block.

11 more elements

Abstract

Claims8