Semiconductor memory device storing data and parity bit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTetsushi Tanizaki
Life of this patent
Estimating the term…
Abstract
A DRAM includes a plurality of first memory arrays and a second memory array. The plurality of first memory arrays are arranged in two lines. The second memory array is provided on one end side of a region including memory arrays. Each of first memory arrays is divided into four blocks, and performs 1/4 divisional operation. The second memory array is divided into four blocks and performs 1/2 divisional operation. Refresh operation of the DRAM can be switched to 1024 refresh cycle and 512 refresh cycle. Each of the first memory arrays includes 1024 word lines, and the second memory array includes 512 word lines corresponding to the 512 refresh cycle.
Claims15
A semiconductor memory device formed on a chip, comprising:
- a plurality of first memory arrays arranged in at least two columns each including a plurality of first memory cells;
- a second memory array;
- and
- addressing means for accessing said plurality of first memory arrays and said second memory array in parallel;
- wherein
- said plurality of first memory cells of each first memory array are arranged in a plurality of columns and a plurality of rows and said each first memory array is divided into a first number of blocks arranged in a column direction for divisional operation,
- said second memory array includes a plurality of second memory cells arranged in a plurality of columns aligned with the plurality of columns of said plurality of first memory cells, and is divided into a second number of blocks arranged in a column direction for divisional operation, the number of columns in each block being greater than the number of rows,
- said second number is no greater than half of said first number, and
- said plurality of first memory cells included in each of said first number of blocks and the second memory cells included in each of said second number of blocks are arranged in the same number of rows.
A semiconductor memory device formed on a semiconductor chip having first and second pairs of sides, said first pair of sides being substantially parallel and said second pair of sides being substantially parallel, comprising:
- a plurality of first memory arrays arranged in 2m lines in parallel with said second pair of sides with m representing a positive integer;
- a second memory array;
- and
- addressing means for accessing said second memory array and each of said first memory arrays in parallel, wherein
- each of said plurality of first memory arrays includes memory cells arranged in a plurality of columns and plurality of rows, and is divided into 4mn blocks arranged in parallel with said second pair of sides, with n representing a positive integer,
- said second memory array includes a plurality of columns of memory cells aligned with respective columns of said 2m lines of said plurality of first memory arrays and is divided into 2n blocks arranged in parallel with said second pair of sides, and
- said memory cells included in each of said 4mn blocks and said memory cells included in each of said 2n blocks being arranged in the same number of rows.
A semiconductor memory device formed on a substantially rectangular semiconductor chip having a first pair of parallel sides and a second pair of parallel sides, longer than said first pair of parallel sides, comprising:
- a plurality of first memory arrays arranged in at least two columns with each column being parallel to said second pairs of parallel sides, each first memory array including a plurality of first memory cells arranged in a plurality of columns and a plurality of rows, and divided in a first number of blocks for divisional operation, the rows of first memory cells of each first number of blocks being parallel to said first pair of parallel sides;
- a second memory array including a plurality of second memory cells arranged in a plurality of columns and a plurality of rows and divided in a second number of blocks for division operation, the plurality of columns of said second memory cells being lined with the plurality of columns of said plurality of first memory cells in said at least two columns of said plurality of first memory arrays, the rows of second memory cells of each second number of blocks being parallel to said first pair of parallel sides;
- and
- addressing means for accessing said plurality of first memory arrays and said second memory array in parallel, wherein
- said second number of blocks is no greater than half said first number of blocks, and
- the number of rows of first memory cells in each of said first number of blocks and the number of rows of second memory cells in each of said second number of blocks are the same.
Dependencies are inferred from the claim text.