Address control system for a RAM in a digital audio set
AssigneeSamsung Electronics Co., Ltd.
InventorByung-Chull Park
Life of this patent
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Abstract
An address control system for a RAM, comprising a synchronous counter for receiving input data according to a clock signal and providing n-bit row column address, and an n-bit column address a first buffer for receiving the n-bit row address from the synchronous counter and generating the n-bit row address, a first tri-state inverter for outputting data stored in a ROM according to a write enable signal a second tri-state inverter for outputting reference data according to the write enable signal, an adder for adding the n-bit column address from the synchronous counter and output address signals from the first inverter, and a second buffer for receiving output signals from the adder generating a column address delayed from the n-bit column address.
Claims15
An address control system for a random access memory, comprising:
- a synchronous counter for receiving input data according to a clock signal and providing an n-bit row address and an n-bit column address;
- a first tri-state buffer for providing said n-bit row address in dependence upon said n-bit row address received from said synchronous counter;
- a first tri-state inverter for receiving and inverting delay data stored in a read only memory according to a write enable signal to generate inverted data;
- a second tri-state inverter for receiving and inverting reference voltage data according to said write enable signal;
- an adder for adding said n-bit column address from said synchronous counter and said inverted data from said first tri-state inverter to generate an added signal;
- and
- a second tri-state buffer for receiving said added signal from said adder and generating a delayed column address delayed by an amount of time based on said delay data.
An address control system for controlling and delaying a read address and a write address of a random access memory, said address control system comprising:
- synchronous counting means for generating a row address and a column address in response to a clock signal;
- first tri-state inverting means for receiving and inverting delay data in response to a write enable signal to generate first inverted data on a first plurality of output lines;
- second tri-state inverting means for receiving and inverting a reference voltage in response to said write enable signal to generate second inverted data on said first plurality of output lines;
- adding means for adding said column address to said first inverted data to generate an added signal;
- first tri-state buffer means for storing and transmitting said row address on a second plurality of output lines in response to a row address strobe signal;
- and
- second tri-state buffer means for storing said added signal and transmitting said added signal on said second plurality of output lines in response to a column address strobe signal.
An address control system for controlling and delaying read addresses and write addresses of a random access memory in a digital audio system, said address control system comprising:
- counting means for generating a row address and a column address in response to a clock signal;
- means for alternately enabling transmission of one of delay data and reference voltage data in response to a write enable signal to generate a time lag signal;
- adding means for adding said column address to said time lag signal to generate an added signal;
- and
- means for alternately enabling transmission of one of said row address and said added signal in response to a column address strobe signal and a row address strobe signal.
A method of controlling and delaying a read/write address of a random access memory in a digital audio system, said method comprising:
- generating a row address and a column address in response to a clock signal;
- adding a delay signal to said column address during a read mode of the random access memory to generate a first added signal;
- adding a reference voltage signal to said column address during a write mode of the random access memory to generate a second added signal;
- and
- generating said read/write address by alternately enabling transmission of said row address and one of said first added signal and said second added signal to the random access memory in response to a row address strobe signal and a column address strobe signal.
Dependencies are inferred from the claim text.