Control apparatus for data storage apparatus

A control apparatus for a data storage apparatus comprising:

• first and second memory elements having a power supply terminal and a chip select terminal, for storing data;
• access means for accessing said first and second memory elements;
• said access means comprising an MPU (MICROPROCESSOR UNIT) for outputting an access signal and a chip select signal for accessing said memory elements and a power supply for generating a first normal operation voltage and a second data hold voltage which is lower than said first normal operation voltage;
• first and second voltage switch means for switching said first and second memory elements between a normal operation voltage state and a data hold voltage state with a lower voltage than said normal operation voltage state;
• said first and second switch means respectively comprising voltage change-over switch circuits for selectively supplying the power supply terminal of the respective memory elements with said first normal operation voltage and said second data hold voltage and chip select mask gates coupled to receive chip select signals corresponding to said respective memory elements from said MPU for setting the respective chip select terminal of said first and second memory elements in a select or non-select state;
• and
• control means for detecting access conditions of said first and second memory elements based on an access signal from said MPU constituting said access means;
• said control means comprising switching signal generating circuits for outputting switching signals for switching said first and second voltage switch means to said normal operation voltage mode when said first and second memory elements are accessed while switching the same to said low data hold voltage mode when said first and second memory elements are not accessed, and circuits for controlling said chip select mask gates so as to set said chip select terminal in the select state when said first and second memory elements are accessed and controlling to mask said chip select signal so as to set said chip select terminals in the non-select state when said memory elements are not accessed,
• characterized by switching said switching means to either of the normal operation mode with the normal operation voltage and the data hold mode with a low electric power consumption in accordance with access conditions of said first and second memory elements.

A control apparatus for a data storage apparatus comprising:

• a plurality of memory elements having a first access terminal and a second access terminal;
• access means for accessing said plurality of memory elements;
• said access means comprising an MPU (MICROPROCESSOR UNIT) for outputting respective access signals and a byte enable signal for accessing said plurality of memory elements and a controller for outputting access signals and a refresh signal based on an access request generated from said MPU;
• a plurality of said switching means for switching said first and second access terminals of said memory elements between a normal electric power consumption state and a low electric power consumption state in which an electric power consumption is lower than said normal electric power consumption state;
• said switching means comprising switch circuits coupled to receive a switching signal, said access signal and said refresh signal for setting the access terminals of said memory elements in an active state with a predetermined electric power consumption when said switching signal is at high level or when said access signals or said refresh signal is active while switching the same to an inactive state with a low electric power consumption when said signals are in states other than those mentioned above;
• control means for detecting access conditions of said memory elements based on an access signal from the MPU constituting said access means and controlling said switch circuits to said normal electric power consumption state when said memory elements are accessed while switching the same to said low electric power consumption state when said memory elements are not accessed;
• said control means comprising switching signal generating circuits for outputting said switching signals corresponding to said accessed memory elements to said switch circuits when said memory elements are accessed,
• characterized by controlling said change-over switch circuits, when any of the plurality of said memory elements is accessed, such that all or at least a portion of the remaining memory elements are set in said low electric power consumption mode.

A control apparatus for a data storage apparatus comprising:

• a dynamic random access memory (DRAM) for storing data, the DRAM having an access terminal to which an access signal having a first level and an access signal having a second level different from the first level are selectively supplied, the access signal having the first level placing the DRAM in a normal electric power consumption state wherein the DRAM can be accessed, and the access signal having the second level placing the DRAM in a low electric power consumption state wherein the DRAM cannot be accessed;
• a microprocessor (MPU) for outputting a DRAM access request signal indicating that at least one of a plurality of DRAMs is to be accessed, the plurality of DRAMs including the DRAM, and for outputting a byte enable signal having a first level when the DRAM is included in that at least one of the plurality of DRAMs to be accessed and having a second level different from the first level when the DRAM is not included in that at least one of the plurality of DRAMs to be accessed;
• control means for outputting a DRAM access signal having a first level when the MPU is outputting the DRAM access request signal and having a second level different from the first level when the MPU is not outputting the DRAM access request signal, for outputting a refresh signal having a first level when the DRAM is to be refreshed and having a second level different from the first level when the DRAM is not to be refreshed, and for outputting a switching signal having a first level when the byte enable signal from the MPU has the first level and having a second level different from the first level when the byte enable signal from the MPU has the second level;
• and
• switching means for supplying the access signal having the first level to the access terminal of the DRAM when the DRAM access signal has the first level and the switching signal has the first level or when the refresh signal has the first level, thereby switching the DRAM to the normal electric power consumption state wherein the DRAM can be accessed, and for otherwise supplying the access signal having the second level to the access terminal of the DRAM, thereby switching the DRAM to the low electric power consumption state wherein the DRAM cannot be accessed.

A control apparatus for a data storage apparatus comprising:

• a plurality of memory elements for storing data, each memory element of the plurality of memory elements having a first access terminal and a second access terminal to which a first access signal and a second access signal are respectively supplied so as to selectively place the corresponding memory element in an active normal electric power consumption state wherein the corresponding memory element can be accessed and an inactive low electric power consumption state wherein the corresponding memory element cannot be accessed;
• a microprocessor (MPU) for outputting a memory access request signal indicating that at least one memory element of the plurality of memory elements is to be accessed, and for outputting a byte enable signal indicating which memory element or memory elements of the plurality of memory elements is or are to be accessed;
• control means for outputting a third access signal and a fourth access signal indicating whether or not at least one memory element of the plurality of memory elements is to be accessed based on the memory access request signal, for outputting a refresh signal indicating whether or not the plurality of memory elements are to be refreshed, and for outputting a respective switching signal for each memory element of the plurality of memory elements indicating whether or not the corresponding memory element is to be accessed based on the byte enable signal;
• and
• switching means including a respective switching circuit for each memory element of the plurality of memory elements, the respective switching circuit supplying the first access signal and the second access signal to the first access terminal and the second access terminal, respectively, of the corresponding memory element so as to place the corresponding memory element in the active normal electric power consumption state or the inactive low electric power consumption state based on the third access signal, the fourth access signal, the refresh signal, and the respective switching signal such that when at least one memory element of the plurality of memory elements is in the active normal electric power consumption state, at least one other memory element of the plurality of memory elements is in the inactive low electric power consumption state.