Semiconductor non-volatile memory device improved in verifying operation for erased and write-in states
AssigneeNEC Corporation
InventorsToshiya Sato, Kazuhisa Ninomiya
Life of this patent
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Abstract
When an electrically erasable and program read only memory device enters an erasing mode of operation, electrons are evacuated from floating gate electrodes of the floating gate type field effect transistors serving as memory cells, and the evacuation is continued over a time period instructed from an internal memory circuit so that the memory cells are prevented from depletion mode due to excess evacuation as well as from non-erased state due to insufficient evacuation.
Claims5
A semiconductor non-volatile memory device fabricated on a single semiconductor chip and having at least an erasing mode, a write-in mode and a read-out mode of operation, comprising:
- a) a plurality of memory cells for storing electrically erasable data bits;
- b) a timer means for storing an interval data indicative of a time period determined through an inspection sequence for said plurality of memory cells for appropriately allowing most of said plurality of memory cells to enter an erased state, and producing an enable signal until said time period is expired;
- and
- c) an erasing means responsive to an external instruction code indicative of an erasing mode of operation, and enabled with said enable signal for erasing said electrically erasable data bits stored in said plurality of memory cells, thereby causing most of said plurality of memory cells to enter said erased state.
Dependencies are inferred from the claim text.