Early row address strobe (RAS) precharge
AssigneeInternational Business Machines Corporation
InventorsRobert M. Blake, William P. Hovis, David J. Perlman
Life of this patent
Estimating the term…
Abstract
In a memory system, which includes a dynamic random access memory (DRAM) that has to be precharged before the contents thereof can be selectively read out into a static register, there is provided means for reading the memory contents of the memory cells of a part or the whole of a row of memory cells of the DRAM into the static register while concurrently precharging the DRAM for a subsequent read-out command. This reduces the overall cycle time of the memory array since read-out of the static register can occur during precharge.
Claims13
A memory system, which includes a random access memory array whose contents are selectively read out to a static register, the memory system comprising:
- means coupled to the memory array and within the static register for receiving and statically storing a predetermined number of data bits read out from the memory array upon the receipt of a read-out command;
- and
- enabling means coupled to the static register and to the memory array for enabling the read-out of the contents of the static register and for concurrently precharging the memory array to prepare the memory array for a subsequent read-out command.
In combination:
- a memory array of data storage elements;
- a static register for statically storing selected bits read-out from the memory array into the static register;
- and
- signal generating means, which is responsive to a read-out command, coupled to the memory array and to the static register for:
- a) enabling the memory array and the read-out of selected data from the memory array into the static register for a time period which begins shortly after receipt of the read-out command and extends for a time TR thereafter;
- b) resetting the memory array after the time TR, and preparing it for the next read-out command during a subsequent time period TP which is sufficient to precharge the memory array and to prepare the memory array for a next read out;
- and
- c) enabling the contents of the static register to be read-out for a period of time which extends beyond the time TR and extends into the subsequent time period ,TP, during which the memory array is being prepared for the next read-out.
A memory system including a memory array whose contents are selectively read out to a register, the memory system comprising:
- means responsive to a read-out command coupled to said memory array and to said register for enabling a predetermined number of data bits to be read out from said memory array and to be stored in said register;
- and
- said means including means coupled to said register and to said memory array for placing said memory in a precharge condition to prepare the memory array for the next read-out command following the transfer of said predetermined number of bits to said register;
- and, while precharging said memory array, enabling the continued read-out of the contents of said register for a selected period of time.
Dependencies are inferred from the claim text.