US 5,297,090 AGranted

Semiconductor memory with column decoded bit line equilibrate

AssigneeSGS-Thomson Microelectronics S.A.

InventorDavid C. McClure

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Abstract

A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V , and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns. In an additional embodiment of the invention, a data transition detection circuit also controls the precharge and equilibration transistors, so that the precharge and equilibration transistors for the selected columns are turned on responsive to an input data transition during a write operation; this assists the write drivers in more quickly writing the new data onto the bit lines.

Claims19

Dependent claims

A memory in an integrated circuit, comprising:

a plurality of memory cells arranged in rows and columns;
a plurality of pairs of bit lines, each associated with one of said columns, for communicating a differential signal from a selected memory cell in its associated column;
a row decoder for selecting, responsive to a row address, a plurality of memory cells for connection with their associated pair of bit lines;
a plurality of equilibration transistors, each associated with a pair of bit lines, having a conduction path connected between its associated bit lines, and having a control terminal;
a column decoder for selecting a column in said array responsive to a column address;
and
means for controlling the control terminals of said equilibration transistors according to said column address in such a manner that each of said equilibration transistors is conductive responsive to its associated column being not selected, and in such a manner that each of said equilibration transistors is not conductive responsive to its associated column being selected so that the selected memory cell in the selected column places a differential signal on its associated bit lines without opposition from a DC load;
wherein said controlling means is also for controlling the control terminals of said equilibration transistors in such a manner that each of said equilibration transistors is conductive responsive to a transition in either said row address or in said column address.

5 more elements

Dependencies are inferred from the claim text.