Methods and devices for accelerating failure of marginally defective dielectric layers

A method of stressing a semiconductor memory device to induce failure of marginally defective dielectric layers within the semiconductor memory device, the memory device having a plurality of row lines;

• a plurality of column lines, and a common storage cell plate;
• the common storage cell plate being connected to a reference voltage;
• the row lines being selectively connectable to a row line voltage;
• the column lines being selectively connectable to the reference voltage;
• the method comprising the following steps:
• increasing the magnitude of the row line voltage beyond that which occurs during memory access operations;
• decreasing the magnitude of the reference voltage beyond that which occurs during memory access operations;
• and
• simultaneously connecting the increased-magnitude row line voltage to a plurality of row lines and the decreased-magnitude reference voltage to a plurality of column lines.

A method of stressing a semiconductor memory device to induce failure of marginally defective dielectric layers within the semiconductor memory device;

• the memory device having a plurality of row lines, a plurality of column lines, and a common storage cell plate;
• the storage cell plate being connected to a reference voltage;
• the memory device having at least one equilibrate circuit connected to selectively bias the column lines to the reference voltage;
• the memory device also including a row line voltage source which provides a row line voltage, and a row line decoder to selectively connect the row line voltage to the row lines during memory access operations;
• the method comprising the following steps:
• supplying a row line stress voltage to the row line voltage source to increase the magnitude of the row line voltage beyond that which occurs during memory access operations;
• generating a stress mode signal within the memory device in response to the increased-magnitude row line voltage being supplied;
• activating the row line decoder in response to the stress mode signal to simultaneously bias all of the row lines to the increased-magnitude row line voltage;
• decreasing the magnitude of the reference voltage in response to the stress mode signal;
• and
• activating the equilibrate circuit in response to the stress mode signal to bias a plurality of the column lines to the decreased-magnitude reference voltage.

A semiconductor memory device comprising:

• a plurality of row lines;
• a plurality of column lines;
• a common storage cell plate;
• a cell plate generator which produces a reference voltage, the reference voltage being connected to the common storage cell plate;
• a row line voltage source which produces a row line voltage;
• a test pad to receive an externally-supplied stress voltage, the stress voltage being received by the row line voltage source to increase the magnitude of the row line voltage beyond that which occurs during memory access operations;
• a stress mode detection circuit which receives the stress voltage and generates a stress mode signal in response;
• a row decoder which selectively biases individual row lines to the row line voltage during memory access operations, the row decoder being responsive to the stress mode signal to simultaneously bias a plurality of the row lines to the increased-magnitude row line voltage;
• and
• at least one equilibrate circuit connected to receive the reference voltage from the cell plate generator and being responsive to the stress mode signal to simultaneously bias a plurality of the column lines to the reference voltage.