Semiconductor memory device with redundant block and cell array

A static random access memory device, comprising:

• a plurality of normal blocks each having a plurality of normal memory cells arranged in matrix form of normal rows and columns, each normal column having a pair of normal bit lines between which normal memory cells arranged in respective normal columns are connected;
• a redundant block having a plurality of redundant memory cells arranged in redundant rows and columns of equal numbers to said normal rows and columns of each of the respective normal blocks, each redundant column having a pair of redundant bit lines between which redundant memory cells arranged in respective redundant columns are connected, said redundant bit line pairs being for replacing defective normal bit line pairs;
• means for providing first selecting signals and second selecting signals in response to first address signals;
• normal column decoding means, associated with respective ones of said normal blocks, for selecting defect-free normal bit line pairs, when said normal bit line pairs are designated by second address signals, in response to said second address signals and said second selecting signals, said normal column decoding means being disabled by redundant control signals when defective normal bit line pairs are designated;
• redundant column decoding means, responsive to said second address signals, and said first selecting signals, for respectively selecting redundant bit line pairs corresponding to the respective defective normal bit line pairs and providing redundant operating signals;
• and
• means for generating said redundant control signals in response to said redundant operating signals.

A semiconductor memory device, comprising:

• a plurality of normal blocks, each having a plurality of normal memory cells arranged in normal rows and columns;
• a redundant block having a plurality of redundant memory cells arranged in redundant rows and columns, said redundant rows and columns being equal in number to said normal rows and columns in respective normal blocks;
• block decoding means for generating block selecting signals to enable selection of one of the normal blocks in response to first address signals;
• redundant column decoding means, responsive to said block selecting signals and second address signals, for selecting redundant columns corresponding to said defective normal columns and generating redundant operating signals;
• redundant clock generating means, responsive to said redundant operating signals, for producing redundant control signals;
• and
• normal column decoding means associated with the normal columns of the respective normal blocks, for enabling replacement of defective normal columns of the respective normal blocks with redundant columns from the redundant block, said normal column decoding means being disabled by said redundant control signals upon said replacement.

A semiconductor memory device, comprising:

• a plurality of normal blocks each having normal memory cells arranged in a set number of normal rows and columns;
• a redundant block having redundant memory cells arranged in said set number of redundant rows and columns, said respective redundant columns being for replacement of defective normal columns;
• first generating means, operably connected to receive first address signals and a first control signal, for producing first selecting signals and second selecting signals therefrom;
• first decoding means, associated with respective ones of said normal blocks, for decoding said second selecting signals to select normal columns therein in response to second address signals, and said second selecting signals;
• second decoding means, operably connected to receive said first selecting signals and said second address signals, for decoding said first selecting signals when a selected normal column is defective, to select a redundant column corresponding thereto and for providing redundant operating signals;
• and
• second generating means for producing said first control signal in response to said redundant operating signals, whereby said first decoding means are all disabled upon the replacement.

A semiconductor memory device, comprising:

• a plurality of normal blocks each containing a plurality of normal memory cells, and having a plurality of normal row lines and normal column lines connected to said normal memory cells;
• a redundant block containing a plurality of redundant memory cells, and having a plurality of redundant row lines and redundant column lines connected to said redundant memory cells, said redundant row lines and redundant column lines being respectively equal in number to said normal row lines and normal column lines of each normal block;
• first decoder means for providing block selecting signals to enable selection of one of said plurality of normal blocks in response to first address signals;
• second decoder means programmable for selecting substitute column lines from among said plurality of redundant column lines in response to said block selecting signals and second address signals and for producing redundant operational signals in response to addressing of defective ones of said plurality of normal memory cells;
• generating means for producing redundant control signals in response to said redundant operational signals;
• and
• third decoder means associated with corresponding ones of said normal memory cells, disabled by said redundant control signals when said defective ones of said plurality of normal memory cells are addressed, for selecting said normal column lines in response to said second address signals.