Sense amplifier in semiconductor memory device

A sense amplifier in a semiconductor memory device having plural memory cells arranged in corresponding rows and columns, at least one pair of bit lines coupled to the plurality of memory cells of a column thereof and plural word lines connected to the plurality of memory cells of the respectively corresponding rows, comprising:

• detection means for generating complementary state signals exhibiting the respective states of a pair of bit lines coupled to the plurality of memory cells of a corresponding column in the semiconductor memory device and to each of which corresponding word lines are coupled;
• an input circuit comprising first and second transistors having corresponding bases thereof connected in common and having the corresponding emitters thereof connected to respective, first and second independent power sources and respectively connected to and receiving the complementary state signals generated by the detection means, the input circuit amplifying the complementary state signals independently of each other and producing as the outputs thereof corresponding, amplified complementary state signals;
• and
• latch means, operatively coupled to said input circuit, for receiving said amplified complementary state signals and a reference voltage signal and for inverting the respective states of the received and amplified complementary state signals and outputting the inverted complementary state signals only when the voltage level of one of said received and amplified complementary state signals decreases to a level lower than the voltage level of said reference voltage signal.