Static semiconductor memory device for stable operation

A semiconductor memory device of a static type achieving information read and write operations according to a content specified by an address, comprising:

• memory cells which are connected to a predetermined word lines respectively related thereto and which are connected to predetermined first and second digit lines respectively associated therewith,
• each said memory cell including a flip flop circuit for storing and keeping therein information and a first gate circuit and a second gate circuit which respectively connect the flip flop circuit to a first digit line and a second digit line in a respective manner according to a potential of the word line;
• and
• word line selector circuits connected to predetermined word lines respectively associated therewith,
• each said word line selector circuit selecting one of the word lines related thereto in response to the address signal by a voltage of said word line,
• each said word line selector including a booster circuit for increasing a voltage of the word line to produce a higher first level and a lower second level for a write operation and a read operation, respectively;
• said booster circuit including:
• a first booster section including two inverters and a capacitor connected in series thereto,
• the series connection of said two inverters and said capacitor being connected in parallel to the word line;
• and
• a second booster section including a second capacitor which is selectively connected to said first capacitor according to a write signal in a write operation.