Square-root operating circuit adapted to perform a square-root at high speed and apply to both of binary signal and quadruple signal
AssigneeSharp Kabushiki Kaisha
InventorYukihiro Yoshida
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Abstract
A square-root operating circuit performs square-root at high speed and applies to both a binary signal and a quadruple signal. The square-root operating circuit includes X.sup.2 circuits, the performing unit, and adding circuits. The X.sub.2 circuits performs a square of an input signal. The performing unit is arranged to perform the square of a candidate square-root of any one of an originally quadruple logic input signal and a quadruple logic input signal converted from a binary logic. The adding circuits compare the input signal with a square of a candidate square-root at each digit and output a result of the comparison so as to discriminate a proper digit of the square-root.
Claims21
A square-root operating circuit adapted to perform a square-root at high speed of both a binary signal and a quadruple signal, comprising:
- means for performing a square of an input signal, said performing means arranged to perform said square of a candidate square-root of any one of an originally quadruple logic input signal and a quadruple logic input signal converted from binary logic;
- and
- means for comparing said input signal with said square of the candidate square-root at each digit and for outputting a result of each comparison so as to discriminate a proper digit of said square-root.
A square-root method adapted to be used in a square-root operating circuit for obtaining a square-root by executing an operation n times at maximum, said square-root operating circuit having a plurality of circuits, each of said plurality of circuits including an AND logic element, an OR logic element, and a register, said square-root operating circuit further having a 2n-bit S register for storing a value to be operated, S, an X register for storing a candidate value X of the square-root, and a W register for storing a square result W, said value S to be operated and said candidate value X of a square root being stored in corresponding registers in sequence from the most significant digits, said square-root method comprising the steps of:
- (1) determining whether said value S is negative;
- (2) determining whether an error takes place, said error occurring when said value S is determined as negative;
- (3) setting a value of 3 as a candidate value of said square root to digits X2i and X2i-1 of said X register;
- (4) squaring said candidate value X to get X.sup.2 and substituting X.sup.2 for W;
- (5) determining whether S.gtoreq.W;
- (6) determining said value of 3 as said digits of said square-root if S.gtoreq.W;
- (7) setting a value of 2 as a candidate value of said square-root to digits X2i and Xwi-1 of said X register if S<W;
- (8) squaring said candidate value X to get X.sup.2 and substituting X.sup.2 for said square result W;
- (9) determining whether S.gtoreq.W;
- (10) determining said value of 2 as said digits of said square-root if S.gtoreq.W;
- (11) setting a value of 1 as a candidate value of said square-root to digits X2i and X2i of said X register if S<W;
- (12) squaring said candidate value X to get X.sup.2 and substituting X.sup.2 for said square result W;
- (13) determining whether S.gtoreq.W;
- (14) determining said value of 1 as said digits of said square-root if S.gtoreq.W;
- (15) setting a value of 0 as a candidate value of said square-root to digits X2i and X2i-1 of said X register if S<W;
- and
- (16) repeating said steps (3) to (15) decrementing i from n to 1.
A square-root method adapted to be used in a square-root operating circuit for obtaining a square-root by executing an operation n times a maximum, said square-root operating circuit having a plurality of circuits, each of said plurality of circuits including an AND logic element, an OR logic element, and a register, said square-root operating circuit further having a 2n-bit S register for storing a value to be operated S, an X register for storing a candidate value X of the square-root, and a W register for storing a square result W, said value S to be operated and said candidate value X of the square-root being stored in corresponding registers in sequence from the most significant digits, said square-root method comprising the steps of:
- (1) determine whether said value S is negative;
- (2) determining whether an error takes place, said error occurring when said value S is determined as negative;
- (3) setting a value of 3 as a candidate value of said square root to digits X2i and X2i-1 of said X register;
- (4) squaring said candidate value X to get X.sup.2 and substituting X.sup.2 for said square result W;
- (5) determining whether S=W;
- (6) terminating said square-root method if S=W;
- (7) determining whether S>W if S.noteq.W;
- (8) determining a value of 3 as said digits of said square-root if S>W;
- (9) setting a value of 2 as a candidate value of said square-root to digits X2i and X2i-1 of said X register if S.ltoreq.W;
- (10) squaring said candidate value X to get X.sup.2 and substituting X.sup.2 for said square result W;
- (11) determining whether S=W;
- (12) terminating said square-root method if S=W;
- (13) determining whether S>W if S.noteq.W;
- (14) determining a value of 2 as said digits of said square-root if S>W;
- (15) setting a value of 1 as a candidate value of said square root to digits X2i and X2i-1 of said X register if S.ltoreq.W;
- (16) squaring said candidate value X to get X.sup.2 and substituting X.sup.2 for said square result W;
- (17) determining whether S=W;
- (18) terminating said square-root method if S=W;
- (19) determining whether S>W if S.noteq.W;
- (20) determining a value of 1 as said digits of said square-root if S>W;
- (21) setting a value of 0 as a candidate value of said square-root to digits X2i and X2i-1 of said X register if S.ltoreq.W;
- and
- (22) repeating said steps (3) to (21) decrementing i from n to 1.
Dependencies are inferred from the claim text.