Directly-writable digital potentiometer

An integrated circuit, comprising:

• first, second, and third signal terminals;
• a passive resistor string having multiple tap points, and having endpoints connected to said first and third signal terminals;
• a plurality of switching devices respectively connected to said multiple tap points and to said second signal terminal;
• and
• control circuitry, connected
• to receive a digital signal, over a serial port, indicating a desired resistance value, said serial port including lines generally corresponding to clock, data, and reset signals;
• and to control said switching devices so that one of said tap points of said resistor string having said desired resistance value to said first signal terminal, is electrically connected to said second terminal;
• wherein said control circuitry can serially shift in data signals when said reset line is in a first state, and will change the state of said switching devices, in accordance with said data signals, when said reset line transitions from said first state to a second state.

An integrated circuit, comprising:

• first and second signal terminals;
• a passive resistor string having multiple tap points;
• a plurality of switching devices respectively connected to ones of said multiple tap points and to said second signal terminal;
• control circuitry, comprising
• a serial port interface, connected to receive digital signals indicating a desired resistance value, said serial port including lines generally corresponding to clock, data, and reset signals;
• a shift register, connected to store and propagate digital data values received over said serial port, and to serially propagate said data values therethrough when said reset line is in a first state;
• parallel control register circuitry, connected to hold digital data values from said shift register in parallel, when said reset line transitions from said first state to a second state;
• and
• decoder/driver logic, connected to control said switching devices in accordance with the digital data values in said parallel control register circuitry;
• and
• a data output buffer, connected to receive data shifted through said serial shift register.

An integrated circuit, comprising:

• first and second signal terminals;
• a passive resistor string having multiple tap points;
• a plurality of switching devices respectively connected to ones of said multiple tap points and to said second signal terminal;
• and
• control circuitry, connected
• to receive a digital signal, over a serial port, indicating a desired resistance value, said serial port including lines generally corresponding to clock, data, and reset signals;
• and to control said switching devices so that a portion of said resistor string, having said desired resistance value, is electrically interposed between said first and second terminals;
• wherein said control circuitry can serially shift in data signals when said reset line is in a first state, and will change the state of said switching devices, in accordance with said data signals, when said reset line transitions from said first state to a second state.

A system, comprising multiple variable-resistance integrated circuits each respectively comprising:

• a passive resistor string having multiple tap points;
• and a plurality of switching devices respectively connected to ones of said multiple tap points;
• control circuitry, comprising:
• a serial port interface, including lines generally corresponding to clock, data, and reset signals;
• a shift register, connected to store and propagate digital data values received over said serial port, and to serially propagate said data values therethrough when said reset line is in a first state;
• parallel control register circuitry, connected to hold digital data values from said shift register in parallel, when said reset line transitions from said first state to a second state;
• and decoder/driver logic, connected to control said switching devices in accordance with the digital data values in said parallel control register circuitry, to connect a selected one of said tap points to an external terminal;
• and a data output buffer, connected to receive data shifted through said serial shift register;
• reset and clock lines connected to each of said variable-resistance chips in parallel;
• and said variable-resistance integrated circuits being daisy-chained together serially, with said data input lines of said serial port of one said integrated circuit being connected to said output buffer of another said integrated circuit.