Method and apparatus for deferred package assignment for components of an electronic circuit for a printed circuit board
AssigneeComputervision Corporation
InventorsMark D. Pease, William Anderson, Jr.
Life of this patent
Estimating the term…
Loading patent…
AssigneeComputervision Corporation
InventorsMark D. Pease, William Anderson, Jr.
Estimating the term…
A computer aided design tool provides a user with the capability of generating a design implementation for electronic circuitry. In this system the user generates a design schematic specifying a functional description of a design for electronic circuitry without the need for specifying packaging information. The system is provided with a packaging tool for generating a physical package for the circuitry of the design schematic. Use of the packaging tool may be deferred until the design schematic has been completed and verified. Further, a user of the system has the option of specifying certain packaging information when creating the design schematic or delaying such specification until just prior to packaging of the design.
A computer aided design system, comprising:
A computer implemented method of deferring packaging of a design for electronic circuitry, comprising the steps of:
A data processing system comprising:
A computer aided design system, comprising:
Dependencies are inferred from the claim text.