Address generating method, and circuit therefor

Abstract

An address generating circuit for generating addresses capable of scanning two-dimensionally arrayed data in zigzag fashion includes an up/down counter for generating addresses in the column direction of the two-dimensional array, an up/down counter for generating addresses in the row direction of the two-dimensional array, and a circuit block for detecting, based upon a three-bit column address and a three-bit row address outputted by respective ones of the counters, whether an address is situated on an edge portion of the two-dimensional array, and for producing an up-count control signal and a down-count control signal of each counter in accordance with the results of detection. This makes it possible to generate addresses that are capable of scanning the two-dimensionally arrayed data in zigzag fashion. Also disclosed is a method of generating addresses using this circuit.

Dependencies are inferred from the claim text.