Improved two-stage analog-to-digital converter

An apparatus for generating a digital signal in response to an analog signal, said analog signal having a magnitude, said digital signal being representative of said magnitude;

• the apparatus comprising:
• a reference means for establishing a reference array;
• said reference means being operatively arranged to receive a reference signal, said reference array including a plurality of first reference values representative of said reference signal, said plurality of first reference values being hierarchically arranged;
• a first comparing means for first iteration comparing said plurality of first reference values with said analog signal;
• said first comparing means generating a first iteration output signal representing an order estimate of said magnitude, each of said plurality of first reference values having an associated adjacent plurality of second reference values, each said associated plurality of second reference values being hierarchically arranged spanning an associated hierarchical interval;
• a logic means for generating output signals in response to received signals;
• said logic means receiving said first iteration output signal and generating a control signal in response to said first iteration output signal;
• and
• a second comparing means for second iteration comparing said associated plurality of second reference values with said analog signal;
• each said associated plurality of second reference values establishing a range of intermediate representations of said reference signal within said associated hierarchical interval, said second comparing means including a pluralityof comparator means for comparing a selected first input signal with a second input signal, each of said plurality of comparator means receiving said analog signal as said first input signal;
• each comparator means comprising first and second transistors, said first transistors being coupled to said second transistors and said logic means, said control signal being applied to said first transistors, and said second reference values being applied to respective gates of said second transistors, where said second reference values as said second input values, and said comparator means compares said first and second input values in response to said control signal;
• said second comparing means generating a second iteration output signal representing said second iteration comparing, said second iteration output signal representing a hierarchical resolving value of said analog signal within said interval associated with a particular first reference value of said plurality of first reference values;
• said logic means receiving said second iteration output signal and operatively responding to said first iteration output signal and said second iteration output signal according to a second predetermined relationship to generate said digital signal.

A circuit for converting an analog signal to a digital signal comprising:

• an analog signal input;
• first and second reference terminals;
• a voltage reference circuit including a series of nodes coupled between the reference terminals, where the circuit is configured to produce reference voltages at each node, with the reference voltages at the nodes increasing from the first node to the last node in the series;
• at least one comparator coupled to the signal input and an intermediate node in the series, where a first set of at least two of the nodes lay between the intermediate node and the first reference terminal and a second set of at least two of the nodes lay between the intermediate node and the second reference terminal;
• a logic circuit including a first logic output, a second logic output, a first logic input coupled to the comparator, where the logic circuit is configured to output a first signal at the first logic output when an input signal at the signal input is greater than the voltage at the intermediate node and output a second signal at the second logic output when the input signal is less than the voltage at the intermediate node, the logic circuit further including second and third logic inputs and a digital output;
• a first comparator circuit coupled to the second logic input and the analog signal input, the first comparator circuit including first and second transistors wherein transistor is connected to another node of the first set, the second transistor is coupled to the first logic output, and the first comparator circuit is configured to output a first comparison signal to the second logic input when the voltage at the one node is above a first predetermined limit;
• and
• a second comparator circuit coupled to the third logic input and the analog signal input, the second compartor circuit including third and fourth transistors wherein where the gate of the third transistor is connected to another node of the first set, the fourth transistor is coupled to the second logic output, and the second comparator circuit is configured to output a second comparison signal to the third logic input when the voltage at the another node is above a second predetermined limit;
• the logic circuit being configured to output a digital signal at the digital output representative of a voltage at the analog input based upon the status of the logic inputs.