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US 5,296,760 AGranted
Voltage translator
AssigneeMotorola, Inc.
InventorsKent C. Oertle, Jia S. Chiang
Life of this patent
Estimating the term…
Abstract
A differential ECL signal is converted to a first current and a second current that are proportional to the ECL signal. An upper output transistor (16) and a lower output transistor (57) are selectively enabled and disabled by the first current. The second current is used to enable discharging of a storage capacitance of the lower output transistor (57) thereby substantially disabling the lower output transistor (57) before the upper output transistor (16) is enabled. In addition, a capacitor is used to momentarily discharge the storage capacitance as the upper output transistor (16) is enabled. The capacitor is discharged when the upper output transistor (16) is disabled.
Claims18
A voltage translator comprising:
- a differential amplifier having a pair of differential inputs and a pair of differential outputs that produce an amplified signal;
- a current mirror having a pair of mirror inputs coupled to the pair of differential outputs and also having a first current output and a second current output wherein the first current output and the second current output each produce a current that is proportional to a voltage applied to the differential inputs;
- a clamp circuit that clamps the first current output to a predetermined voltage when the first current output has a current value that is less than a current value of the second current output;
- a phase splitter transistor having a control electrode coupled to the first current output, a first current electrode coupled to a first terminal of a first resistor, and a second current electrode;
- a second terminal of the first resistor connected to a voltage supply terminal;
- a first transistor having a control electrode coupled to a first terminal of a second resistor, a first current electrode coupled to the second current electrode of the phase splitter transistor, and a second current electrode coupled to a voltage return;
- a second terminal of the second resistor coupled to the second current output;
- a lower output transistor having a control electrode coupled to the first current electrode of the first transistor, a first current electrode coupled to the voltage return, and a second current electrode;
- an a.c. coupled Miller killer circuit having a Miller output coupled to the control electrode of the lower output transistor, and a Miller input that is capacitively coupled to the Miller output;
- an upper Darlington transistor including a second transistor and a third transistor, wherein the second transistor has a control electrode coupled to the first current electrode of the phase splitter transistor, a first current electrode coupled to a first current electrode of the third transistor, a second current electrode coupled to a control electrode of the third transistor, and a third current electrode coupled to the Miller input;
- an output terminal of the voltage translator coupled to a second current electrode of the third transistor and to the second current electrode of the lower output transistor;
- a third resistor having a first terminal coupled to the Miller input, and a second terminal;
- and
- a first diode having an anode coupled to the second terminal of the third resistor, and a cathode coupled to the output terminal.
11 more elements
A voltage translator comprising:
- a first current output and a second current output that each produce a current that is proportional to a signal applied to a pair of differential inputs;
- a first transistor having a control electrode coupled to the first current output, a first current electrode, and a second current electrode;
- a second transistor having a control electrode coupled to a first terminal of a first resistor, a first current electrode coupled to the first current electrode of the first transistor, and a second current electrode coupled to a power supply return;
- a second terminal of the first resistor coupled to the second current output;
- a lower output transistor having a control electrode coupled to the first current electrode of the first transistor, a first current electrode coupled to the power supply return, and a second current electrode;
- an upper output transistor including a third transistor and a fourth transistor wherein the third transistor has a control electrode coupled to the second current electrode of the first transistor, a first current electrode coupled to a first current electrode of the fourth transistor, a second current electrode coupled to a control electrode of the fourth transistor, and a third current electrode coupled to a capacitor;
- and
- an output terminal of the voltage translator coupled to a second current electrode of the fourth transistor and to a second current electrode of the lower output transistor.
5 more elements
A method of translating an ECL signal to a TTL signal comprising:
- converting a differential ECL signal to a first current and a second current that are proportional to the ECL signal;
- selectively switching an upper output transistor and a lower output transistor between a disabled state and an enabled state wherein the switching is controlled by the first current;
- discharging a storage capacitance of the lower output transistor during the enabled state of the upper output transistor wherein the discharging is enabled by the second current;
- capacitively coupling a voltage change on a current electrode of the upper transistor to the lower output transistor for momentarily discharging the storage capacitance of the lower output transistor, the current electrode coupled to a capacitor wherein the capacitor does not degrade switching speed of the upper output transistor;
- and
- discharging the capacitor when the upper output transistor is disabled.
3 more elements
Dependencies are inferred from the claim text.