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US 5,296,758 AGranted
Output buffer with ground bounce compensation
AssigneeNational Semiconductor Corporation
InventorBal S. Sandhu
Life of this patent
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AssigneeNational Semiconductor Corporation
InventorBal S. Sandhu
Estimating the term…
A ground bounce compensating output buffer for an integrated circuit is disclosed. The circuit includes a pull-up transistor, the gate of the pull-up transistor is coupled to an input line, the output of the pull-up transistor is coupled to an output line. The pull-up transistor discharges current to ground during a state transition. The discharge of current to ground creates ground bounce due to the resistance and inductance of the package lead. A pull-down transistor is also provided. The gate of the pull-down transistor is also coupled to the input line, the output of the pull-down transistor is also coupled to the output line. The pull-down transistor also discharges current to ground during a state transition and thereby produces ground bounce. To reduce the ground bounce, the disclosed circuit includes compensating devices positioned between the input line and the gate of the pull-down transistor. The first compensating device includes a mechanism for regulating drive current to the pull-down transistor in the presence of ground bounce. A second compensating device limits voltage to the first compensating device in the presence of ground bounce. As a result, the second compensating device further regulates drive current to the pull-down transistor during ground bounce. A third compensating device generates a constant drive current to the pull-down transistor in the presence of ground bounce. The design of the circuit provides optimal signal delays to minimize totem pole current which would otherwise produce additional ground bounce.
A ground bounce compensating output buffer comprising:
In an output buffer including an input line and a pull-up transistor with a pull-up driver therebetween, and a pull-down transistor with one or more pull-down drivers therebetween, said pull-down transistor being coupled to a logical ground node, said output buffer producing increased voltage on said logical ground node during a state transition of said pull-up transistor, the improvement comprising:
An output buffer for reducing ground bounce, comprising:
A method of compensating for ground bounce in an output buffer, said method comprising the steps of:
Dependencies are inferred from the claim text.