High speed BI CMOS logic circuit and a semiconductor integrated circuit device using same

A semiconductor device comprising:

• a plurality of word lines;
• a plurality of pairs of data lines;
• a plurality of memory cells coupled to said plurality of word lines and to said plurality of pairs of data lines so that each memory cell is coupled to one of said word lines and one of said plurality of pairs of data lines;
• and
• a plurality of word driver circuits coupled to said plurality of word lines, respectively, for bringing one of said plurality of word lines into a selection state,
• wherein each of said plurality of word driver circuits includes:
• a first supply terminal;
• a second supply terminal;
• input bipolar transistors each having a base coupled to receive one of a plurality of input signals, respectively, a collector and an emitter, the collectors of said input bipolar transistors being coupled to one another, the emitters of said input bipolar transistors being coupled to one another, said plurality of input signals having a logic high level or a logic low level;
• P-channel MOSFETs having their gates coupled to the bases of said input bipolar transistors, respectively, and their source-drain paths coupled in series between a first supply terminal and the commonly coupled collectors of said input bipolar transistors;
• N-channel MOSFETs having their gates coupled to the bases of said input bipolar transistors, respectively, and their source-drain paths coupled between the commonly coupled emitters of said input bipolar transistors and said second supply terminal, respectively;
• an output terminal coupled to a corresponding one of said word lines;
• an output bipolar transistor having a collector-emitter path coupled between said first supply terminal and said output terminal and a base coupled to said commonly coupled collectors of said input bipolar transistors;
• an output N-channel MOSFET having a source-drain path coupled between said output terminal and said second supply terminal and a gate coupled to said commonly coupled emitters of said input bipolar transistors;
• and
• level clamp means coupled between said first supply terminal and said base of said output bipolar transistor for clamping a voltage level of said base of said output bipolar transistor at a predetermined voltage when at least one of said plurality of input signals is at said logic high level.

A logic circuit comprising:

• a first input terminal coupled to receive a first input signal having a logic high level or a logic low level;
• a second input terminal coupled to receive a second input signal having a logic high level or a logic low level;
• a first supply terminal coupled to receive a first supply voltage;
• a second supply terminal coupled to receive a second supply voltage;
• a first output terminal for supplying a first output signal;
• a second output terminal for supplying a second output signal;
• a first bipolar transistor having a collector-emitter path coupled between said first supply terminal and said second supply terminal and a base coupled to said first input terminal;
• a second bipolar transistor having a collector-emitter path connected in parallel with said collector-emitter path of said first bipolar transistor and a base coupled to said second input terminal;
• a third bipolar transistor having a collector-emitter path coupled between said first supply terminal and said second supply terminal and a base coupled to receive a reference potential, wherein said third bipolar transistor has its emitter commonly coupled to the emitters of said first and second bipolar transistors;
• first variable impedance means connected between said first supply terminal and the collectors of said first and second bipolar transistors, wherein said first variable impedance means has a low impedance value when both said first input signal and said second input signal are at said logic low level and a high impedance value when at least one of said first input signal and said second input signal is at said logic high level;
• second variable impedance means connected between said first supply terminal and said collector of said third bipolar transistor, wherein said second variable impedance means has a high impedance value when both said first input signal and said second input signal are at said logic low level, and a low impedance value when at least one of said first input signal and said second input signal is at said logic high level;
• a fourth bipolar transistor having a collector-emitter path coupled between said first supply terminal and said first output terminal and a base coupled to said collector of said third bipolar transistor;
• a fifth bipolar transistor having a collector-emitter path coupled between said first supply terminal and said second output terminal and a base coupled to the collectors of said first and second bipolar transistors;
• first charge extracting means connected between said first output terminal and said second supply terminal, wherein said first charge extracting means discharges a first load capacitance coupled to said first output terminal;
• second charge extracting means connected between said second output terminal and said second supply terminal, wherein said second charge extracting means discharges a second load capacitance coupled to said second output terminal;
• and
• a first N-channel MOSFET having a drain source path coupled between commonly coupled emitters of said first, second and third bipolar transistors and said second supply terminal, and a gate coupled to receive a first predetermined voltage.

A logic circuit comprising:

• a first input terminal coupled to receive a first input signal having a logic high level and a logic low level;
• a second input terminal coupled to receive a second input signal which is a phase inverted signal of said first input signal;
• a first supply terminal coupled to receive a first supply voltage;
• a second supply terminal coupled to receive a second supply voltage;
• a first bipolar transistor having a base coupled to said first input terminal, a collector and an emitter;
• a second bipolar transistor having a base, a collector and an emitter;
• first variable impedance means coupled between said first supply terminal and said collector of said first bipolar transistor and having a relatively low impedance value when said first input signal is at said logic low level and a relatively high impedance value when said first input signal is at said logic high level,
• wherein said first variable impedance means includes a first P-channel MOSFET having a gate coupled to said first input terminal and a source-drain path coupled between said first supply terminal and said collector of said first bipolar transistor, and first level clamp means connected in parallel with said source-drain path of said first P-channel MOSFET for clamping a voltage level of said collector of said first bipolar transistor in response to a logic low level at said first input signal;
• second variable impedance means coupled between said first supply terminal and said collector of said second bipolar transistor and having a relatively high impedance value when said first input signal is at said logic low level and a relatively low impedance value when said first input signal is at said logic high level,
• wherein said second variable impedance means includes a second P-channel MOSFET having a gate coupled to said second input terminal and a source-drain path coupled between said first supply terminal and said collector of said second bipolar transistor, and second level clamp means connected in parallel with said source-drain path of said second P-channel MOSFET for clamping a voltage level of said collector of said second bipolar transistor in response to a logic high level at said first input signal;
• and
• a MOSFET having a gate coupled to receive a first predetermined voltage and having a drain-source path coupled between a common emitter connection of said first and second bipolar transistors and said second supply terminal.

A logic circuit comprising:

• a first input terminal coupled to receive a first input signal having a logic high level and a logic low level;
• a first supply terminal coupled to receive a first supply voltage;
• a second supply terminal coupled to receive a second supply voltage;
• a first bipolar transistor having a base coupled to said first input terminal, a collector and an emitter;
• a second bipolar transistor having a base, a collector and an emitter;
• first variable impedance means coupled between said first supply terminal and said collector of said first bipolar transistor and having a relatively low impedance value when said first input signal is at said logic low level and a relatively high impedance value when said first input signal is at said logic high level;
• second variable impedance means coupled between said first supply terminal and said collector of said second bipolar transistor and having a relatively high impedance value when said first input signal is at said logic low level and a relatively low impedance value when said first input signal is at said logic high level;
• and
• a MOSFET having a gate coupled to receive a first predetermined voltage and having a drain-source path coupled between a common emitter connection of said first and second bipolar transistors and said second supply terminal,
• wherein said first variable impedance means includes a first P-channel MOSFET having a gate coupled to said collector of said second bipolar transistor and a source-drain path coupled between said first supply terminal and said collector of said first bipolar transistor, and first level clamp means for clamping a voltage level of said collector of said first bipolar transistor in response to a logic low level at said input signal, said first level clamp means including a second P-channel MOSFET having a source coupled to said first supply terminal, a drain coupled to said collector of said first bipolar transistor and a gate coupled to receive a second predetermined voltage, and
• wherein said second variable impedance means includes a third P-channel MOSFET having a gate coupled to said collector of said first bipolar transistor and a source-drain path coupled between said first supply terminal and said collector of said second bipolar transistor, and second level clamp means for clamping a voltage level of said collector of said second bipolar transistor in response to a logic high level at said input signal, said second level clamp means including a fourth P-channel MOSFET having a source coupled to said first supply terminal, a drain coupled to said collector of said second bipolar transistor and a gate coupled to receive said second predetermined voltage.