US 5,296,752 A · Current memory cell

Abstract

A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first switch (S1) connects a PMOS transistor (P1) as a diode during the sample interval and as a current source during the hold interval. During the sample interval the current in the current terminal (5) is mirrored to the PMOS transistor (P1). During the hold interval the current of the PMOS transistor is mirrored to the current terminal. The mirroring is effected by means of two NMOS transistors (N1, N2) and one reversing switch (S2), which reverses the input and output of the current mirror circuit between the sample intervals and the hold intervals. The current mirror circuit (N1, N2) and the PMOS current source (P1) collectively behave as a current sink which is insensitive to the substrate voltages which are caused by the body effect.

Claims21

Dependent claims

A current memory cell for applying to a current terminal, during a hold interval, an output current which is substantially equal to an input current forced onto the current terminal during a sample interval preceding the hold interval, comprising:

a first current terminal,
a first transistor having a source, a drain and a gate, the drain being coupled to the first current terminal,
a capacitor connected between the source and gate of the first transistor, and
a first switch for coupling the gate of the first transistor to the first current terminal during the sample interval, characterized in that the current memory cell further includes:
a second current terminal,
second and third transistors of a conductivity type opposite to that of the first transistor and each having a source, drain and gate, the drain of the second transistor being coupled to the first current terminal and the drain of the third transistor to the second current terminal, the gate of the second transistor being connected to the gate of the third transistor and gate-source circuits of the second and third transistors being connected in parallel, and
a second switch for coupling the gates of the second and third transistors to the first current terminal during the hold interval and to the second current terminal during the sample interval.

4 more elements

a first current terminal,
a first transistor having a source, a drain and a gate, the drain being coupled to the first current terminal,
a capacitor connected between the source and gate of the first transistor and
a switch for coupling the gate of the first transistor to the first current terminal during the sample interval, characterized in that the current memory cell further includes:
a second current terminal,
second and third transistors of a conductivity type opposite to that of the first transistor and each having a source, drain and gate, the drain of the second transistor being coupled to the first current terminal and the drain of the third transistor to the second current terminal, the gate of the second transistor being connected to the gate of the third transistor and gate-source circuits of the second and third transistors being connected in parallel,
means for creating a substantially constant voltage difference between the gate of the third transistor and the second current terminal and,
a bias current source coupled to the second current terminal.

5 more elements

A current memory cell for sampling a current during a sample interval and for supplying a corresponding current during a hold interval, comprising:

first and second terminals for a supply voltage,
a first current terminal,
a first transistor having a control electrode,
first means for coupling said first current terminal to the first supply voltage terminal via said first transistor,
a capacitor connected between the control electrode and a first main electrode of the first transistor,
a first switch for coupling and decoupling the first transistor control electrode to and from the first current terminal during the sample interval and the hold interval, respectively,
a second current terminal,
second and third transistors of a conductivity type opposite to that of the first transistor and having their control electrodes interconnected,
second means for coupling the first current terminal to the second supply voltage terminal via the second transistor,
third means for coupling the second current terminal to the second supply voltage terminal via the third transistor, and
a second switch for coupling the interconnected control electrodes of the second and third transistors to the first current terminal during the hold interval and to the second current terminal during the sample interval.

8 more elements

A current memory cell for sampling a current during a sample interval and for supplying a corresponding current during a hold interval, comprising:

first and second terminals for a supply voltage,
a first current terminal,
a first transistor having a control electrode,
first means for coupling said first current terminal to the first supply voltage terminal via said first transistor,
a capacitor connected between the control electrode and a first main electrode of the first transistor,
a switch for coupling and decoupling the first transistor control electrode to and from the first current terminal during the sample interval and the hold interval, respectively,
a second current terminal,
second and third transistors of a conductivity type opposite to that of the first transistor and having their control electrodes interconnected,
second means for coupling the first current terminal to the second supply voltage terminal via the second transistor,
third means for coupling the second current terminal to the second supply voltage terminal via the third transistor,
a source of bias current coupled to the second current terminal, and
means for maintaining a substantially constant voltage difference between the control electrode of the third transistor and the second current terminal.

9 more elements

Dependencies are inferred from the claim text.

Current memory cell

Life of this patent

Current memory cell

Life of this patent

Abstract

Claims21