Double gate FET and process for manufacturing same

A process for manufacturing an FET in a semiconductor substrate having a main surface, comprising the steps of:

• forming a buried doped region within the semiconductor substrate, the buried doped region having an upper surface at least adjacent to the main surface of the semiconductor substrate and comprising a first gate, the semiconductor substrate being of a first conductivity type and the first gate being of a second conductivity type opposite to the first conductivity type;
• depositing a first semiconductor layer of the first conductivity type on the main surface of the semiconductor substrate, a portion of the first semiconductor layer disposed above the first gate comprising a channel region having opposite ends, the first gate and the channel region forming a pn junction;
• forming a mask layer, localized on the channel region portion of the first semiconductor layer and thereby disposed above the first gate;
• depositing a second semiconductor layer on the first semiconductor layer, using the mask layer as a mask, the second semiconductor layer being of the second conductivity type and forming source and drain regions respectively in contact with the opposite ends of the channel region;
• removing the localized mask layer thereby to expose an upper surface of the channel region;
• forming a gate insulating layer on the exposed upper surface of the channel region;
• and
• forming a gate electrode on the gate insulating layer and thereby above, and insulated from, the channel region by the gate insulating layer.

A process for manufacturing an FET, comprising the steps of:

• forming a buried doped region within the semiconductor substrate, the buried doped region having an upper surface at least adjacent to the main surface of the semiconductor substrate and comprising a first gate, the semiconductor substrate being of a first conductivity type and the first gate being of a second conductivity type opposite to the first conductivity type;
• depositing a first semiconductor layer on the semiconductor substrate, the first semiconductor layer comprising a central portion having opposite edges and first and second end portions respectively at the opposite edges thereof and integral with the central portion, the central portion being disposed over the first gate and of the first conductivity type and comprising a channel region, the first gate and the channel region forming a pn junction;
• forming a gate insulating layer on the first semiconductor layer;
• forming a gate electrode on the gate insulating layer, localized above the channel region;
• and
• locally doping the first and second end portions of the first semiconductor layer with a dopant of the second conductivity type, using the gate electrode as a mask, thereby to form respective source and drain regions of the second conductivity type.

An FET comprising:

• a semiconductor substrate;
• a first insulating layer formed on the semiconductor substrate;
• a first semiconductor layer formed on the first insulating layer, the first semiconductor layer comprising a first gate of a first conductivity type;
• a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer comprising a central portion having opposite edges and first and second end portions respectively at the opposite edges thereof and integral with the central portion, the central portion being disposed over the first gate and of a second conductivity type opposite to the first conductivity type and comprising a channel region, the first gate and the channel region forming a pn junction;
• a gate insulating layer formed on the channel region;
• a gate electrode formed on the gate insulating layer, localized above the channel region;
• and
• source and drain regions formed in association with the second semiconductor layer and respectively in contact with said opposite ends of the channel region, the source and drain regions being of the first conductivity type.

A process for manufacturing an FET in a semiconductor substrate having a main surface, comprising the steps of:

• forming an insulating layer on the main surface of the substrate;
• forming a first semiconductor layer on the insulating layer, the first semiconductor layer being of a first conductivity type;
• forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer comprising a central portion having opposite edges and first and second end portions respectively at the opposite edges thereof and integral with the central portion, the central portion being disposed over the first gate and of a second conductivity type and comprising a channel region, the first gate and the channel region forming a pn junction;
• forming a gate insulating layer on the second semiconductor layer;
• forming a gate electrode on the gate insulating layer, localized above the channel region;
• and
• locally doping surface regions of the first and second end portions of the second semiconductor layer with a dopant of the first conductivity type, using the gate electrode as a mask, thereby to form respective source and drain regions of the first conductivity type.