Method for manufacturing a DRAM having a second effective capacitor area

A method of manufacturing a semiconductor memory device having a plurality of memory cells each provided with a capacitor, comprising the steps of:

• forming a plurality of spaced field oxide films over a semiconductor substrate for each memory cell, depositing a first insulating film over a portion of said semiconductor substrate above which said capacitor is to be formed, forming a first plate electrode over said first insulating film, and a first dielectric film over said first plate electrode;
• depositing a first charge storage electrode over said first dielectric film and depositing a second insulating film over the entire exposed upper surface of the resultant structure after said step of depositing said first charge storage electrode;
• exposing a portion of said semiconductor substrate over which said field oxide films are not formed, and depositing a polysilicon film over both said exposed semiconductor substrate portion and a portion of the second insulating film which is disposed over first charge storage electrode, to form a polysilicon substrate;
• forming, on said polysilicon substrate, a field effect transistor including an active region, a gate insulating film and a gate electrode, and forming a word line on the second insulating film simultaneously with the formation of said gate electrode;
• depositing a third insulating film over the entire exposed upper surface of the resultant structure after the formation of said field effect transistor, partially exposing both said active region and said first charge storage electrode and forming a second charge storage electrode on a portion of said third insulating film such that it is connected with said exposed portions of the active region and first charge storage electrode;
• depositing a second dielectric film over said second charge storage electrode and depositing a plate electrode over said second dielectric film;
• and
• depositing a fourth insulating film over the entire exposed surface of the resultant structure after the deposition of said plate electrode and forming a bit line in contact with the active region.